专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US09437677B2 Deposition on a nanowire using atomic layer deposition 有权
标题翻译：使用原子层沉积在纳米线上沉积
公开(公告)号：US09437677B2
公开(公告)日：2016-09-06
申请号：US13604739
申请日：2012-09-06
申请人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
发明人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
IPC分类号： H01L29/775 , B82Y99/00 , H01L29/06 , H01L21/84 , H01L27/12 , H01L29/47 , H01L29/66 , H01L29/78 , B82Y30/00 , B82Y40/00 , B82Y10/00 , H01L51/00 , H01L51/05
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/42392 , H01L29/47 , H01L29/6675 , H01L29/7839 , H01L51/0048 , H01L51/0516 , H01L51/0558 , H01L51/057 , Y10S977/762 , Y10S977/938
摘要： A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.
摘要翻译：半导体器件包括衬底，纳米线，第一结构和第二结构。纳米线悬挂在第一结构和第二结构之间，其中第一结构和第二结构超过衬底，其中纳米线包括纳米线表面上的层，其中该层包括硅化物和碳化物中的至少一种，其中该层具有基本均匀的形状。

82. 发明授权

US09059006B2 Replacement-gate-compatible programmable electrical antifuse 有权
标题翻译：替换门兼容可编程电气反熔丝
公开(公告)号：US09059006B2
公开(公告)日：2015-06-16
申请号：US13523120
申请日：2012-06-14
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L23/52 , H01L29/10 , H01L27/06 , H01L23/525 , H01L27/112 , H01L29/66 , H01L29/49 , H01L29/78
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触点中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

83. 发明授权

US08927432B2 Continuously scalable width and height semiconductor fins 有权
标题翻译：连续可调的宽度和高度半导体鳍片
公开(公告)号：US08927432B2
公开(公告)日：2015-01-06
申请号：US13523048
申请日：2012-06-14
申请人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
发明人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845
摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.
摘要翻译：通过为鳍式场效应晶体管所采用的半导体鳍片的物理尺寸提供两个独立的变量，可以为鳍式场效应晶体管提供任意和连续的可变电流。在掩埋绝缘体层上的半导体层上形成凹陷区域。在半导体层上形成电介质盖层。在电介质盖层上形成一次性心轴结构，并且围绕一次性心轴结构形成间隔结构。在掩蔽离子注入期间，选择的间隔结构可以在结构上受损。使用蚀刻以比未损坏的间隔物结构更大的蚀刻速率去除结构损坏的间隔物结构。在去除一次性心轴结构之后，将半导体层图案化成具有不同高度和/或不同宽度的多个半导体翅片。随后可以形成具有不同宽度和/或高度的鳍场效应晶体管。

84. 发明授权

US08859316B2 Schottky junction si nanowire field-effect bio-sensor/molecule detector 有权
标题翻译：肖特基结si纳米线场效应生物传感器/分子检测器
公开(公告)号：US08859316B2
公开(公告)日：2014-10-14
申请号：US12825527
申请日：2010-06-29
申请人： Dechao Guo , Christian Lavoie , Christine Ouyang Qiqing , Yanning Sun , Zhen Zhang
发明人： Dechao Guo , Christian Lavoie , Christine Ouyang Qiqing , Yanning Sun , Zhen Zhang
IPC分类号： H01L21/00 , H01L29/06 , G01N27/414
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/0673
摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.
摘要翻译：肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

85. 发明授权

US08753964B2 FinFET structure having fully silicided fin 有权
标题翻译： FinFET结构具有完全硅化的翅片
公开(公告)号：US08753964B2
公开(公告)日：2014-06-17
申请号：US13015123
申请日：2011-01-27
申请人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
发明人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
IPC分类号： H01L29/786
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/76895 , H01L29/66795 , H01L29/7843 , H01L29/785
摘要： A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.
摘要翻译：一种半导体器件，其包括在半导体衬底上形成的半导体材料的散热片，然后形成在鳍片上并与翅片接触的栅电极。绝缘体层沉积在栅电极和鳍片上。然后在绝缘体层中蚀刻沟槽开口。沟槽开口暴露翅片并在翅片之间延伸。然后将鳍片通过沟槽开口硅化。然后，沟槽开口填充有与硅化物翅片接触的金属，以形成连接翅片的局部互连。

86. 发明授权

US08729637B2 Work function adjustment by carbon implant in semiconductor devices including gate structure 有权
标题翻译：通过碳植入在包括栅极结构的半导体器件中进行功能调整
公开(公告)号：US08729637B2
公开(公告)日：2014-05-20
申请号：US13253268
申请日：2011-10-05
申请人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
发明人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
IPC分类号： H01L21/70 , H01L21/20 , H01L21/00
CPC分类号： H01L27/092 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/28194 , H01L21/823857 , H01L29/1054 , H01L29/517
摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
摘要翻译：一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。还公开了形成上述装置的方法。

87. 发明申请

US20130330899A1 PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING 审中-公开
标题翻译：防止高K金属加工过程中的完全硅化物形成
公开(公告)号：US20130330899A1
公开(公告)日：2013-12-12
申请号：US13527063
申请日：2012-06-19
申请人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
发明人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
IPC分类号： H01L21/336 , H01L21/04
CPC分类号： H01L29/78 , H01L29/4966 , H01L29/51 , H01L29/665 , H01L29/66628
摘要： A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.
摘要翻译：一种形成用于晶体管器件的栅叠层结构的方法包括在衬底上形成栅介电层; 在所述栅极介电层上形成第一硅栅极层; 在所述第一硅栅极层上形成富含掺杂剂的单层; 以及在所述富掺杂剂单层上形成第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。

88. 发明授权

US08605499B2 Resonance nanoelectromechanical systems 有权
标题翻译：共振纳米机电系统
公开(公告)号：US08605499B2
公开(公告)日：2013-12-10
申请号：US13092247
申请日：2011-04-22
申请人： Leland Chang , Michael A. Guillorn , Dechao Guo , Fei Liu , Keith Kwong Hon Wong
发明人： Leland Chang , Michael A. Guillorn , Dechao Guo , Fei Liu , Keith Kwong Hon Wong
IPC分类号： G11C11/50
CPC分类号： H03H9/2457 , G11C11/404 , G11C23/00 , H03H2009/02314
摘要： Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions.
摘要翻译：用栅电极操作纳米级悬臂梁的系统和方法。示例性系统包括耦合到栅电极的驱动电路，其中来自电路的驱动信号可以使光束在光束的共振频率处或其附近振荡。驱动信号包括AC分量，并且还可以包括DC分量。替代示例系统包括纳米级悬臂梁，其中光束振荡以接触多个漏极区域。

89. 发明申请

US20130264653A1 STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS 有权
公开(公告)号：US20130264653A1
公开(公告)日：2013-10-10
申请号：US13443133
申请日：2012-04-10
申请人： Ming Cai , Dechao Guo , Liyang Song , Chun-Chen Yeh
发明人： Ming Cai , Dechao Guo , Liyang Song , Chun-Chen Yeh
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/02532 , H01L21/76224 , H01L21/7624 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1207 , H01L29/0649 , H01L29/16 , H01L29/161
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.

90. 发明授权

US08513131B2 Fin field effect transistor with variable channel thickness for threshold voltage tuning 有权
标题翻译：具有可变通道厚度的Fin场效应晶体管用于阈值电压调谐
公开(公告)号：US08513131B2
公开(公告)日：2013-08-20
申请号：US13050101
申请日：2011-03-17
申请人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
IPC分类号： H01L21/311
CPC分类号： H01L27/0886 , H01L21/3086 , H01L21/845 , H01L27/1211
摘要： A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
摘要翻译：一种形成集成电路（IC）的方法包括在基板上形成第一和第二多个间隔物，其中所述基板包括硅层，并且其中所述第一多个间隔件的厚度不同于所述第二多个间隔物; 并且使用所述第一和第二多个间隔物作为掩模来蚀刻所述衬底中的所述硅层，其中所述蚀刻的硅层形成第一多个和第二多个鳍状场效应晶体管（FINFET）沟道区，并且其中所述第一多个 FINFET通道区域各自具有对应于第一多个间隔物的厚度的相应厚度，并且其中第二多个FINFET沟道区域各自具有对应于第二多个间隔物的厚度的相应厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式