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81. 发明申请

US20080185641A1 Recessed transistor and method of manufacturing the same 有权
标题翻译：嵌入式晶体管及其制造方法
公开(公告)号：US20080185641A1
公开(公告)日：2008-08-07
申请号：US12068179
申请日：2008-02-04
申请人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
发明人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
摘要翻译：提供凹陷晶体管及其制造方法。凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。衬底可以包括建立衬底的有源区和场区的隔离层。衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。源/漏区可以与有源区和栅电极相邻形成。

82. 发明授权

US07384850B2 Methods of forming complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions therein 有权
标题翻译：形成其中具有三维沟道区的互补金属氧化物半导体（CMOS）晶体管的方法
公开(公告)号：US07384850B2
公开(公告)日：2008-06-10
申请号：US11087988
申请日：2005-03-23
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/8234
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/66787 , H01L29/78645
摘要： An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active region has a first channel region therein with a first height. A PMOS transistor is also provided. The PMOS transistor has a second fin-shaped active region that extends in the semiconductor substrate. This second fin-shaped active region has a second channel region therein with a second height unequal to the first height.
摘要翻译：包含互补金属氧化物半导体晶体管的集成电路器件包括半导体衬底和具有在半导体衬底中延伸的第一鳍状有源区的NMOS晶体管。第一鳍形有源区域在其中具有第一高度的第一通道区域。还提供PMOS晶体管。 PMOS晶体管具有在半导体衬底中延伸的第二鳍状有源区。该第二鳍形有源区域具有其中具有不等于第一高度的第二高度的第二沟道区域。

83. 发明授权

US07084478B2 Load resistor with dummy contact substantially free of charge build up during etching process 有权
标题翻译：在蚀刻过程中负载电阻器具有基本上不含电荷的虚拟接触
公开(公告)号：US07084478B2
公开(公告)日：2006-08-01
申请号：US10270563
申请日：2002-10-16
申请人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
发明人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/0802
摘要： A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
摘要翻译：制造具有负载电阻器的半导体器件，使得在负载电阻器的两端形成接触，并且在触点之间形成至少一个触点，以便防止在触点期间在每个触点内产生杂质通过蚀刻绝缘层产生的电荷产生，当蚀刻工艺制造绝缘层以在位于绝缘层下方的长负载电阻器中产生接触并在电和物理上绝缘时产生电荷现象。

84. 发明授权

US07056781B2 Method of forming fin field effect transistor 有权
标题翻译：形成鳍式场效应晶体管的方法
公开(公告)号：US07056781B2
公开(公告)日：2006-06-06
申请号：US11014212
申请日：2004-12-15
申请人： Jae-Man Yoon , Gyo-Young Jin , Hee-Soo Kang , Dong-Gun Park
发明人： Jae-Man Yoon , Gyo-Young Jin , Hee-Soo Kang , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7854 , H01L29/78609
摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.
摘要翻译：根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。侧壁由形成在器件隔离膜上的开口部分部分露出。开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。源极和漏极区域在栅电极不是的有源区域的一部分上。可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。

85. 发明申请

US20050215014A1 Complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions and methods of forming same 有权
标题翻译：具有三维沟道区的互补金属氧化物半导体（CMOS）晶体管及其形成方法
公开(公告)号：US20050215014A1
公开(公告)日：2005-09-29
申请号：US11087988
申请日：2005-03-23
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/66787 , H01L29/78645
摘要： An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active region has a first channel region therein with a first height. A PMOS transistor is also provided. The PMOS transistor has a second fin-shaped active region that extends in the semiconductor substrate. This second fin-shaped active region has a second channel region therein with a second height unequal to the first height.
摘要翻译：包含互补金属氧化物半导体晶体管的集成电路器件包括半导体衬底和具有在半导体衬底中延伸的第一鳍状有源区的NMOS晶体管。第一鳍形有源区域在其中具有第一高度的第一通道区域。还提供PMOS晶体管。 PMOS晶体管具有在半导体衬底中延伸的第二鳍状有源区。该第二鳍形有源区域具有其中具有不等于第一高度的第二高度的第二沟道区域。

86. 发明授权

US06940129B2 Double gate MOS transistors 失效
标题翻译：双栅MOS晶体管
公开(公告)号：US06940129B2
公开(公告)日：2005-09-06
申请号：US10715664
申请日：2003-11-18
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648 , H01L29/78654
摘要： A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.
摘要翻译：双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。半导体柱支撑晶体管有源区，使得晶体管有源区与衬底有源区间隔开。至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。底栅电极与衬底有源区，晶体管有源区和半导体柱绝缘。至少一个顶栅电极跨越晶体管有源区，并且具有与底栅电极的侧壁接触的至少一个端。顶栅电极与底栅电极重叠并与晶体管有源区绝缘。还提供制造这种晶体管的方法。

87. 发明申请

US20050184348A1 Semiconductor device gate structure and method of forming the same 审中-公开
标题翻译：半导体器件栅极结构及其形成方法
公开(公告)号：US20050184348A1
公开(公告)日：2005-08-25
申请号：US11059145
申请日：2005-02-15
申请人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
发明人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L21/823487 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78618 , H01L29/78642
摘要： A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, and a first conductive pattern extends from a lower portion of the channel pattern in a first direction verticalperpendicular to the channel pattern and in parallel with the substrate. A second conductive pattern extends from an upper portion of the channel pattern in a second direction verticalperpendicular to the channel pattern and in parallel with the substrate. Accordingly, the channel length of the MOS transistor is determined by a distance between the first and second conductive patterns, and a channel width of the MOS transistor is determined by a diameter of the gate structure. Short channel and narrow width effects are sufficiently prevented in a MOS transistor.
摘要翻译：公开了一种MOS晶体管，其包括在垂直方向上延伸半导体衬底的栅极结构。栅极结构包括从垂直方向从衬底延伸的栅极电极和围绕栅电极的栅极绝缘层。沟道图案包围栅极绝缘层，并且第一导电图案沿着垂直于沟道图案的第一方向并且与衬底平行地从沟道图案的下部延伸。第二导电图案沿着垂直于沟道图案的第二方向并与衬底平行地从沟道图案的上部延伸。因此，MOS晶体管的沟道长度由第一和第二导电图案之间的距离决定，并且MOS晶体管的沟道宽度由栅极结构的直径决定。在MOS晶体管中充分防止了短沟道和窄宽度效应。

88. 发明申请

US20050176186A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050176186A1
公开(公告)日：2005-08-11
申请号：US11048369
申请日：2005-01-31
申请人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
发明人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/785 , H01L29/7854 , H01L29/78603 , H01L29/78648
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.
摘要翻译：在一个实施例中，半导体器件包括具有下层和覆盖在下层上的上层的半导体衬底。上层被布置和构造成形成彼此间隔开并从下层的上表面突出的第一和第二有源区。桥接形状的第三有源区域与下层的上表面垂直地间隔开并且连接第一和第二有源区域。该器件还包括栅电极，其形成有围绕第三有源区的栅绝缘层，使得第三有源区用作沟道。

89. 发明授权

US09012982B2 Recessed transistor and method of manufacturing the same 有权
标题翻译：嵌入式晶体管及其制造方法
公开(公告)号：US09012982B2
公开(公告)日：2015-04-21
申请号：US12068179
申请日：2008-02-04
申请人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
发明人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
摘要翻译：提供凹陷晶体管及其制造方法。凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。衬底可以包括建立衬底的有源区和场区的隔离层。衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。源/漏区可以与有源区和栅电极相邻形成。

90. 发明授权

US08174065B2 Semiconductor device having vertical transistor and method of fabricating the same 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US08174065B2
公开(公告)日：2012-05-08
申请号：US12840599
申请日：2010-07-21
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L29/66
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

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