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81. 发明授权

US08431471B2 Method for integrating a non-volatile memory (NVM) 有权
标题翻译：用于集成非易失性存储器（NVM）的方法
公开(公告)号：US08431471B2
公开(公告)日：2013-04-30
申请号：US12951862
申请日：2010-11-22
申请人： Jane A. Yater , Sung-Taeg Kang , Mehul D. Shroff
发明人： Jane A. Yater , Sung-Taeg Kang , Mehul D. Shroff
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/105 , H01L27/11531 , H01L27/11548 , H01L27/11573 , H01L27/11575 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/788 , H01L29/792
摘要： A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.
摘要翻译：在NVM器件和逻辑器件的图案化和蚀刻期间，在NVM隔离区域中形成特征，使得该特征与逻辑器件的高度基本相等，并且被明确地限定，使得其不会引起缺陷信号。第一导电层形成在衬底上。图案化第一导电层以在NVM区域和隔离区域的至少一部分中露出衬底的至少一部分。在第一导电层，暴露的衬底和暴露的隔离区上方形成NVM电介质堆叠，并且在NVM电介质叠层上形成第二导电层。图案化第一和第二导电层和NVM电介质叠层以形成NVM区域中的NVM单元的第一栅极和第二栅极以及隔离区域上的特征。该特征包括第一导电层的一部分，与第一导电层的该部分的第一侧壁相邻的NVM电介质堆叠的一部分以及邻近NVM电介质叠层部分的第二导电层的一部分。

82. 发明授权

US08372699B2 Method for forming a split-gate memory cell 有权
标题翻译：形成分裂栅极存储单元的方法
公开(公告)号：US08372699B2
公开(公告)日：2013-02-12
申请号：US12710111
申请日：2010-02-22
申请人： Sung-Taeg Kang , Jane A. Yater
发明人： Sung-Taeg Kang , Jane A. Yater
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/28282 , H01L29/42348 , H01L29/792
摘要： A method for forming a semiconductor device includes forming a first semiconductor layer over a substrate, forming a first photoresist layer over the first semiconductor layer, and using only a first single mask patterning the first photoresist layer to form a first patterned photoresist layer. The method further includes using the first patterned photoresist layer etching the first semiconductor layer to form a select gate and forming a charge storage layer over the select gate and a portion of the substrate. The method further includes forming a second semiconductor layer over the charge storage layer, forming a second photoresist layer over the second semiconductor layer, and using only a second single mask patterning the second photoresist layer to form a second patterned photoresist layer. The method further includes forming a control gate by anisotropically etching the second semiconductor layer and then subsequently isotropically etching the second semiconductor layer.
摘要翻译：一种用于形成半导体器件的方法包括在衬底上形成第一半导体层，在第一半导体层上形成第一光致抗蚀剂层，并且仅使用图案化第一光致抗蚀剂层的第一单掩模形成第一图案化光致抗蚀剂层。该方法还包括使用蚀刻第一半导体层的第一图案化光刻胶层形成选择栅极并在选择栅极和衬底的一部分上形成电荷存储层。该方法还包括在电荷存储层上形成第二半导体层，在第二半导体层上形成第二光致抗蚀剂层，并且仅使用图案化第二光致抗蚀剂层的第二单掩模形成第二图案化光致抗蚀剂层。该方法还包括通过各向异性蚀刻第二半导体层然后随后各向同性蚀刻第二半导体层来形成控制栅极。

83. 发明授权

US08329544B2 Method for forming a semiconductor device having nanocrystals 有权
标题翻译：用于形成具有纳米晶体的半导体器件的方法
公开(公告)号：US08329544B2
公开(公告)日：2012-12-11
申请号：US13085238
申请日：2011-04-12
申请人： Sung-Taeg Kang , Jane A. Yater
发明人： Sung-Taeg Kang , Jane A. Yater
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/28273 , H01L29/66825
摘要： A method is provided for forming a semiconductor device having nanocrystals. The method includes: forming a first insulating layer over a surface of a substrate; forming a first plurality of nanocrystals on the first insulating layer; implanting a first material into the first insulating layer; and annealing the first material to form a second plurality of nanocrystals in the first insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density.
摘要翻译：提供了一种形成具有纳米晶体的半导体器件的方法。该方法包括：在衬底的表面上形成第一绝缘层; 在所述第一绝缘层上形成第一多个纳米晶体; 将第一材料注入第一绝缘层; 以及退火所述第一材料以在所述第一绝缘层中形成第二多个纳米晶体。该方法可用于为具有更大纳米晶体密度的非易失性存储器提供电荷存储层。

84. 发明授权

US07939880B2 Split gate non-volatile memory cell 有权
标题翻译：分闸门非易失性存储单元
公开(公告)号：US07939880B2
公开(公告)日：2011-05-10
申请号：US12103451
申请日：2008-04-15
申请人： Sung-Taeg Kang , Rode R. Mora
发明人： Sung-Taeg Kang , Rode R. Mora
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332
摘要： A non-volatile memory (NVM) cell comprising a layer of discrete charge storing elements, a control gate, and a select gate is provided. The control gate has a first sidewall with a lower portion being at least a first angle 10 degrees away from 90 degrees with respect to substrate. Further, the select gate has a second sidewall with a lower portion being at least a second angle at least 10 degrees away from 90 degrees with respect to the substrate. The NVM cell further comprises a layer of dielectric material located between the first sidewall and the second sidewall.
摘要翻译：提供了包括离散电荷存储元件层，控制栅极和选择栅极的非易失性存储器（NVM）单元。所述控制栅极具有第一侧壁，所述第一侧壁的下部至少相对于衬底离开90度的第一角度为10度。此外，选择栅极具有第二侧壁，其具有相对于衬底的90度至少10度的至少第二角度的至少第二角度。 NVM单元还包括位于第一侧壁和第二侧壁之间的介电材料层。

85. 发明授权

US07871886B2 Nanocrystal memory with differential energy bands and method of formation 有权
标题翻译：具有差分能带的纳米晶体记忆和形成方法
公开(公告)号：US07871886B2
公开(公告)日：2011-01-18
申请号：US12436558
申请日：2009-05-06
申请人： Cheong Min Hong , Sung-Taeg Kang
发明人： Cheong Min Hong , Sung-Taeg Kang
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/02488 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02601 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.
摘要翻译：使用半导体衬底制造半导体器件的方法包括在半导体衬底上形成具有第一带能的第一绝缘层。具有第二带能的第一半导体层形成在第一绝缘层上。第一半导体层被退火以从第一半导体层形成多个第一电荷保持器球。在多个第一电荷保持器球的每个电荷保持器球上形成第一保护膜。在多个第一电荷保持器球上形成具有第三带能的第二半导体层。第二半导体层被退火以在多个第一电荷保持器球上从第二半导体层形成多个存储小球。第二带能量的大小在第一带能量的大小和第三带能量的大小之间。

86. 发明授权

US07800158B2 Semiconductor device and method of forming the same 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US07800158B2
公开(公告)日：2010-09-21
申请号：US11600499
申请日：2006-11-16
申请人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang
发明人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang
IPC分类号： H01L31/032
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/66825 , Y10S257/90
摘要： There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.
摘要翻译：提供了一种半导体器件及其形成方法。半导体器件包括存储器件和自对准选择器件。在自对准选择装置和存储装置之间形成浮点。

87. 发明申请

US20100029052A1 SELF-ALIGNED IN-LAID SPLIT GATE MEMORY AND METHOD OF MAKING 有权
标题翻译：自对准的内部分离器存储器及其制造方法
公开(公告)号：US20100029052A1
公开(公告)日：2010-02-04
申请号：US12181766
申请日：2008-07-29
申请人： Sung-Taeg Kang , Jane A. Yater
发明人： Sung-Taeg Kang , Jane A. Yater
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L21/84 , H01L27/11521 , H01L27/11568 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/7881 , H01L29/792
摘要： A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.
摘要翻译：一种方法包括形成氮化硅层并将其图案化以形成由氮化硅的第一部分分开的第一开口和第二开口。栅极材料沉积在第一和第二开口中以在第一和第二开口中形成第一和第二选择栅极结构。氮化硅层的第二和第三部分分别与第一和第二栅极结构相邻地去除。在去除第二和第三部分之后，在半导体器件上形成电荷存储层。栅极材料的第一和第二侧壁间隔物形成在电荷存储层上并与第一和第二栅极结构相邻。使用第一和第二侧壁间隔物作为掩模蚀刻电荷存储层。第一部分被删除。在第一和第二栅极结构之间的半导体层中形成漏极区。

88. 发明授权

US07521750B2 Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same 有权
标题翻译：具有多位非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US07521750B2
公开(公告)日：2009-04-21
申请号：US12017239
申请日：2008-01-21
申请人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile semiconductor device includes a pair of multi-bit nonvolatile memory unit cells. Each unit cell includes a grid type semiconductor body in which a plurality of parallel semiconductor bodies extend in a first direction and a plurality of parallel semiconductor bodies extend in a second direction perpendicular to the first direction, a channel region formed in a partial region of the semiconductor body along circumferences of the semiconductor bodies that extend in the first direction, a charge storage region formed on the channel region, a plurality of control gates, which are formed on the charge storage region and wherein each of the plurality of control gates is adapted to receive separate control voltages. Each unit cell further includes source and drain regions aligned on both sides of the plurality of control gates and formed in the semiconductor bodies, wherein the pair of unit cells share the source region, and the source region is formed at a cross point of the grid.
摘要翻译：非易失性半导体器件包括一对多位非易失性存储单元。每个单电池包括栅格型半导体本体，其中多个平行的半导体本体在第一方向上延伸，并且多个平行的半导体本体在垂直于第一方向的第二方向上延伸，沟道区形成在半导体本体沿着在第一方向上延伸的半导体本体的周边，形成在沟道区上的电荷存储区域，形成在电荷存储区域上的多个控制栅极，并且其中多个控制栅极中的每一个被适配以接收单独的控制电压。每个单元还包括在多个控制栅极的两侧对准并形成在半导体主体中的源极和漏极区域，其中该对单元电池共享源极区域，并且源极区域形成在栅极的交叉点处。

89. 发明授权

US07339232B2 Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same 有权
标题翻译：具有多位非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US07339232B2
公开(公告)日：2008-03-04
申请号：US11256554
申请日：2005-10-21
申请人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.
摘要翻译：提供具有多位非易失性存储单元的半导体器件。半导体器件包括共享源极和漏极区域并具有多个晶体管的多位非易失性存储单元单元。多个晶体管各自包括至少一个控制栅极和至少一个电荷存储区域。电荷存储区域用于在存储单元的多个晶体管的每一个内累积电荷。每个控制栅极被连接到至少一个控制电压以移位多个晶体管中的每个晶体管中的阈值电压以存储每位单元的多位。

90. 发明申请

US20080020527A1 NON-VOLATILE MEMORY CELL HAVING A SILICON-OXIDE-NITRIDE-OXIDE-SILICON GATE STRUCTURE AND FABRICATION METHOD OF SUCH CELL 审中-公开
标题翻译：具有硅氧烷 - 氮氧化物 - 硅门结构的非挥发性记忆体和这种细胞的制造方法
公开(公告)号：US20080020527A1
公开(公告)日：2008-01-24
申请号：US11833132
申请日：2007-08-02
申请人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
发明人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , G11C16/0466 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/40117 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons can be injected into the charge trapping region by hot electron injection. During an erasing operation, holes can be injected into the charge trapping region. Embodiments of the invention include a charge trapping region that is overlapped by the control gate only to an extent where the electrons that were injected during a programming operation can be erased later by injecting holes in the charge trapping region.
摘要翻译：描述能够沿第一方向写入并沿第二方向读取的非易失性存储单元。存储单元包括位于源极或漏极附近的一个或两个电荷捕获区域，或源极和漏极两者。在编程操作期间，可以通过热电子注入将电子注入电荷俘获区域。在擦除操作期间，可以将空穴注入电荷捕获区域。本发明的实施例包括与控制栅极重叠的电荷捕获区域，只有在编程操作期间注入的电子可以通过在电荷俘获区域中注入空穴而被擦除的程度。

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