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81. 发明授权

US09337072B2 Apparatus and method for substrate clamping in a plasma chamber 有权
标题翻译：用于在等离子体室中进行基板夹持的装置和方法
公开(公告)号：US09337072B2
公开(公告)日：2016-05-10
申请号：US12950105
申请日：2010-11-19
申请人： Ganesh Balasubramanian , Amit Bansal , Eller Y. Juco , Mohamad Ayoub , Hyung-Joon Kim , Karthik Janakiraman , Sudha Rathi , Deenesh Padhi , Martin Jay Seamons , Visweswaren Sivaramakrishnan , Bok Hoen Kim , Amir Al-Bayati , Derek R. Witty , Hichem M'Saad , Anton Baryshnikov , Chiu Chan , Shuang Liu
发明人： Ganesh Balasubramanian , Amit Bansal , Eller Y. Juco , Mohamad Ayoub , Hyung-Joon Kim , Karthik Janakiraman , Sudha Rathi , Deenesh Padhi , Martin Jay Seamons , Visweswaren Sivaramakrishnan , Bok Hoen Kim , Amir Al-Bayati , Derek R. Witty , Hichem M'Saad , Anton Baryshnikov , Chiu Chan , Shuang Liu
IPC分类号： H02N13/00 , H01L21/683 , C23C16/52 , H01J37/32 , H01L21/67
CPC分类号： H01L21/6831 , C23C16/52 , H01J37/32431 , H01L21/67069 , H01L21/67253
摘要： The present invention generally provides methods and apparatus for monitoring and maintaining flatness of a substrate in a plasma reactor. Certain embodiments of the present invention provide a method for processing a substrate comprising positioning the substrate on an electrostatic chuck, applying an RF power between the an electrode in the electrostatic chuck and a counter electrode positioned parallel to the electrostatic chuck, applying a DC bias to the electrode in the electrostatic chuck to clamp the substrate on the electrostatic chuck, and measuring an imaginary impedance of the electrostatic chuck.
摘要翻译：本发明通常提供了用于监测和维持等离子体反应器中的基板的平坦度的方法和装置。本发明的某些实施例提供了一种处理衬底的方法，包括将衬底定位在静电吸盘上，在静电吸盘中的电极与平行于静电吸盘的对置电极之间施加RF功率，将DC偏压施加到静电卡盘中的电极将基板夹在静电卡盘上，并测量静电卡盘的假想阻抗。

82. 发明授权

US08895842B2 High quality TCO-silicon interface contact structure for high efficiency thin film silicon solar cells 有权
标题翻译：高效率薄膜硅太阳能电池的高品质TCO硅接口接触结构
公开(公告)号：US08895842B2
公开(公告)日：2014-11-25
申请号：US12481175
申请日：2009-06-09
申请人： Shuran Sheng , Yong Kee Chae , Stefan Klein , Amir Al-Bayati , Bhaskar Kumar
发明人： Shuran Sheng , Yong Kee Chae , Stefan Klein , Amir Al-Bayati , Bhaskar Kumar
IPC分类号： H01L31/00 , H01L21/00 , H01L31/20 , H01L31/076 , H01L31/0224 , C23C16/24 , H01L31/18
CPC分类号： H01L31/076 , C23C16/24 , H01L31/022466 , H01L31/022483 , H01L31/1824 , H01L31/202 , Y02E10/545 , Y02E10/548 , Y02P70/521
摘要： A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon containing layer formed on the second TCO layer. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first p-i-n junction on the second TCO layer.
摘要翻译：提供一种用于形成太阳能电池的方法和装置。在一个实施例中，光伏器件包括设置在衬底上的第一TCO层，设置在第一TCO层上的第二TCO层和形成在第二TCO层上的p型含硅层。在另一个实施例中，形成光伏器件的方法包括在衬底上形成第一TCO层，在第一TCO层上形成第二TCO层，以及在第二TCO层上形成第一p-i-n结。

83. 发明申请

US20120211164A1 SYSTEMS FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION AND BEVEL EDGE ETCHING 审中-公开
标题翻译：等离子体增强化学气相沉积和水平蚀刻系统
公开(公告)号：US20120211164A1
公开(公告)日：2012-08-23
申请号：US13456080
申请日：2012-04-25
申请人： Ashish Shah , Dale R. DuBois , Ganesh Balasubramanian , Mark A. Fodor , Eui Kyoon Kim , Chiu Chan , Karthik Janakiraman , Thomas Nowak , Joseph C. Werner , Visweswaren Sivaramakrishnan , Mohamad Ayoub , Amir Al-Bayati , Jianhua Zhou
发明人： Ashish Shah , Dale R. DuBois , Ganesh Balasubramanian , Mark A. Fodor , Eui Kyoon Kim , Chiu Chan , Karthik Janakiraman , Thomas Nowak , Joseph C. Werner , Visweswaren Sivaramakrishnan , Mohamad Ayoub , Amir Al-Bayati , Jianhua Zhou
IPC分类号： H01L21/3065 , C23C16/458 , C23C16/50 , H01L21/306
CPC分类号： H01L21/6719 , H01J37/32366 , H01J2237/3321 , H01L21/67201 , H01L21/67207
摘要： Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions.
摘要翻译：本文所述的实施例涉及集成衬底边缘处理能力的衬底处理系统。处理系统的说明性示例包括但不限于工厂接口，负载锁定室，传送室和具有两个或更多个处理区域的一个或多个双处理室，其可彼此隔离并且共享公共气体供应和普通排气泵。每个双处理室中的处理区域包括单独的气体分配组件和RF功率源，以在每个处理区域的衬底表面上的选择性区域提供等离子体。因此，每个双处理室被配置为允许在处理区域中的至少两个基板上同时执行多个隔离过程。

84. 发明授权

US07879683B2 Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay 有权
标题翻译：在电介质层中产生气隙以减少RC延迟的方法和装置
公开(公告)号：US07879683B2
公开(公告)日：2011-02-01
申请号：US11869396
申请日：2007-10-09
申请人： Amir Al-Bayati , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang “David” Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
发明人： Amir Al-Bayati , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang “David” Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/3105 , H01L21/31111 , H01L21/31144 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
摘要翻译：一种用于在互连结构的电介质材料中产生气隙的方法和装置。一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层，在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。

85. 发明申请

US20100051098A1 HIGH QUALITY TCO-SILICON INTERFACE CONTACT STRUCTURE FOR HIGH EFFICIENCY THIN FILM SILICON SOLAR CELLS 有权
标题翻译：高性能TCO硅界面接触结构，用于高效薄膜硅太阳能电池
公开(公告)号：US20100051098A1
公开(公告)日：2010-03-04
申请号：US12481175
申请日：2009-06-09
申请人： Shuran Sheng , Yong Kee Chae , Stefan Klein , Amir Al-Bayati , Bhaskar Kumar
发明人： Shuran Sheng , Yong Kee Chae , Stefan Klein , Amir Al-Bayati , Bhaskar Kumar
IPC分类号： H01L31/00 , H01L31/18
CPC分类号： H01L31/076 , C23C16/24 , H01L31/022466 , H01L31/022483 , H01L31/1824 , H01L31/202 , Y02E10/545 , Y02E10/548 , Y02P70/521
摘要： A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon containing layer formed on the second TCO layer. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first p-i-n junction on the second TCO layer.
摘要翻译：提供一种用于形成太阳能电池的方法和装置。在一个实施例中，光伏器件包括设置在衬底上的第一TCO层，设置在第一TCO层上的第二TCO层和形成在第二TCO层上的p型含硅层。在另一个实施例中，形成光伏器件的方法包括在衬底上形成第一TCO层，在第一TCO层上形成第二TCO层，以及在第二TCO层上形成第一p-i-n结。

86. 发明申请

US20090093128A1 METHODS FOR HIGH TEMPERATURE DEPOSITION OF AN AMORPHOUS CARBON LAYER 审中-公开
标题翻译：非晶碳层高温沉积方法
公开(公告)号：US20090093128A1
公开(公告)日：2009-04-09
申请号：US11868859
申请日：2007-10-08
申请人： MARTIN JAY SEAMONS , Yoganand N. Saripalli , Kwangduk Douglas Lee , Bok Hoen Kim , Visweswaren Sivaramakrishnan , Wendy H. Yeh , Josephine Ju-Hwei Chang Liu , Amir Al-Bayati , Derek R. Witty , Hichem M'Saad
发明人： MARTIN JAY SEAMONS , Yoganand N. Saripalli , Kwangduk Douglas Lee , Bok Hoen Kim , Visweswaren Sivaramakrishnan , Wendy H. Yeh , Josephine Ju-Hwei Chang Liu , Amir Al-Bayati , Derek R. Witty , Hichem M'Saad
IPC分类号： H01L21/47
CPC分类号： H01L21/02115 , C23C16/26 , H01L21/02274 , H01L21/3146 , H01L21/76829
摘要： Methods for high temperature deposition an amorphous carbon film with improved step coverage are provided. In one embodiment, a method for of depositing an amorphous carbon film includes providing a substrate in a process chamber, heating the substrate at a temperature greater than 500 degrees Celsius, supplying a gas mixture comprising a hydrocarbon compound and an inert gas into the process chamber containing the heated substrate, and depositing an amorphous carbon film on the heated substrate having a stress of between 100 mega-pascal (MPa) tensile and about 100 mega-pascal (MPa) compressive.
摘要翻译：提供了高温沉积方法，提供了具有改进的台阶覆盖率的无定形碳膜。在一个实施方案中，沉积非晶碳膜的方法包括在处理室中提供衬底，在大于500摄氏度的温度下加热衬底，将包含烃化合物和惰性气体的气体混合物供应到处理室包含加热的基底，以及在具有100兆帕（拉伸）拉伸和约100兆帕斯卡（MPa）压应力之间的应力的加热基底上沉积无定形碳膜。

87. 发明授权

US07482255B2 Method of ion implantation to reduce transient enhanced diffusion 有权
标题翻译：离子注入法减少瞬时增强扩散
公开(公告)号：US07482255B2
公开(公告)日：2009-01-27
申请号：US11302499
申请日：2005-12-14
申请人： Houda Graoui , Majeed Ali Foad , Amir Al-Bayati
发明人： Houda Graoui , Majeed Ali Foad , Amir Al-Bayati
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/268
摘要： A method of ion implantation comprises the steps of: providing a semiconductor substrate; performing a pre-amorphisation implant in the semiconductor substrate in a direction of implant at an angle in the range of 20-60° to a normal to a surface of the semiconductor substrate, and performing an implant of a dopant in the semiconductor substrate to provide a shallow junction. In a feature of the invention, the method further comprises performing an implant of a defect trapping element in the semiconductor substrate and the pre-amorphisation implant step is performed at a first implant energy and the implant of a defect trapping element is performed at a second implant energy, the ratio of the first implant energy to the second implant energy being in the range of 10-40%.
摘要翻译：离子注入的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底中以与所述半导体衬底的表面的法线成20-60°的范围内的角度在所述半导体衬底中进行预非晶化注入，以及在所述半导体衬底中进行掺杂剂的注入以提供一个浅交界处。在本发明的特征中，该方法还包括在半导体衬底中执行缺陷俘获元件的注入，并且以第一注入能量执行预非晶化注入步骤，并且在第二次执行缺陷俘获元件的注入注入能量，第一注入能量与第二注入能量之比在10-40％的范围内。

88. 发明申请

US20080084650A1 APPARATUS AND METHOD FOR SUBSTRATE CLAMPING IN A PLASMA CHAMBER 审中-公开
标题翻译：用于在等离子体室中衬底夹紧的装置和方法
公开(公告)号：US20080084650A1
公开(公告)日：2008-04-10
申请号：US11866646
申请日：2007-10-03
申请人： Ganesh Balasubramanian , Amit Bansal , Eller Juco , Mohamad Ayoub , Hyung-Joon Kim , Karthik Janakiraman , Sudha Rathi , Deenesh Padhi , Martin Seamons , Visweswaren Sivaramakrishnan , Bok Kim , Amir Al-Bayati , Derek Witty , Hichem M'Saad , Anton Baryshnikov , Chiu Chan , Shuang Liu
发明人： Ganesh Balasubramanian , Amit Bansal , Eller Juco , Mohamad Ayoub , Hyung-Joon Kim , Karthik Janakiraman , Sudha Rathi , Deenesh Padhi , Martin Seamons , Visweswaren Sivaramakrishnan , Bok Kim , Amir Al-Bayati , Derek Witty , Hichem M'Saad , Anton Baryshnikov , Chiu Chan , Shuang Liu
IPC分类号： H01L21/683
CPC分类号： H01L21/6831 , C23C16/52 , H01J37/32431 , H01L21/67069 , H01L21/67253
摘要： The present invention generally provides methods and apparatus for monitoring and maintaining flatness of a substrate in a plasma reactor. Certain embodiments of the present invention provide a method for processing a substrate comprising positioning the substrate on an electrostatic chuck, applying an RF power between the an electrode in the electrostatic chuck and a counter electrode positioned parallel to the electrostatic chuck, applying a DC bias to the electrode in the electrostatic chuck to clamp the substrate on the electrostatic chuck, and measuring an imaginary impedance of the electrostatic chuck.
摘要翻译：本发明通常提供了用于监测和维持等离子体反应器中的基板的平坦度的方法和装置。本发明的某些实施例提供了一种处理衬底的方法，包括将衬底定位在静电吸盘上，在静电吸盘中的电极与平行于静电吸盘的对置电极之间施加RF功率，将DC偏压施加到静电卡盘中的电极将基板夹在静电卡盘上，并测量静电卡盘的假想阻抗。

89. 发明申请

US20070288116A1 METHOD, SYSTEM AND MEDIUM FOR CONTROLLING SEMICONDUCTOR WAFER PROCESSES USING CRITICAL DIMENSION MEASUREMENTS 审中-公开
标题翻译：用于使用关键尺寸测量来控制半导体波长处理的方法，系统和介质
公开(公告)号：US20070288116A1
公开(公告)日：2007-12-13
申请号：US11736350
申请日：2007-04-17
申请人： Amir Al-Bayati , Babak Adibi , Majeed Foad , Sasson Somekh
发明人： Amir Al-Bayati , Babak Adibi , Majeed Foad , Sasson Somekh
IPC分类号： G06F19/00
CPC分类号： H01L21/67253 , H01L22/20
摘要： Methods, systems, and mediums of controlling a semiconductor manufacturing process are described. The method comprises the steps of measuring at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, determining at least one process parameter value on the at least one measured dimension, and controlling at least one semiconductor manufacturing tool to process the at least one of the plurality of wafers based on the at least one parameter value. A variation in the at least one critical dimension causes undesirable variations in performance of the at least one device, and at least one process condition is directed to controlling the processing performed on the plurality of wafers. The at least one manufacturing tool includes at least one of an implanter tool and an annealing tool.
摘要翻译：描述了控制半导体制造工艺的方法，系统和介质。该方法包括以下步骤：测量在至少一个晶片上制造的至少一个器件的至少一个临界尺寸，确定至少一个测量尺寸上的至少一个工艺参数值，以及控制至少一个半导体基于所述至少一个参数值来处理所述多个晶片中的所述至少一个的制造工具。所述至少一个关键尺寸的变化导致所述至少一个装置的性能的不期望的变化，并且至少一个处理条件涉及控制在所述多个晶片上执行的处理。所述至少一个制造工具包括注入机工具和退火工具中的至少一个。

90. 发明申请

US20130242287A1 Process and Apparatus for Measuring the Crystal Fraction of Crystalline Silicon Casted Mono Wafers 有权
标题翻译：用于测量晶体硅铸造单晶硅晶体分数的方法和装置
公开(公告)号：US20130242287A1
公开(公告)日：2013-09-19
申请号：US13421194
申请日：2012-03-15
申请人： Asaf Schlezinger , Amir Al-Bayati
发明人： Asaf Schlezinger , Amir Al-Bayati
IPC分类号： G01N21/59 , G01N21/55
CPC分类号： G01N21/59
摘要： Provided are methods and apparatus for determining the crystal fraction of a casted-mono silicon wafer. A light source is directed at the wafer and the transmission or reflection is measured by a detector. An image of the wafer is generated by a processor and the crystal fraction is calculated from the generated image. The crystal fraction is correlated to the efficiency of the solar cell produced, allowing for the rejection of inferior wafers prior to processing.
摘要翻译：提供了用于确定铸造单晶硅晶片的晶体分数的方法和装置。光源指向晶片，透射或反射由检测器测量。由处理器生成晶片的图像，并根据所生成的图像计算晶体分数。晶体分数与所制造的太阳能电池的效率相关，允许在处理之前排出劣质晶片。

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