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81. 发明授权

US06841883B1 Multi-dice chip scale semiconductor components and wafer level methods of fabrication 失效
标题翻译：多芯片尺寸半导体元件和晶圆级制造方法
公开(公告)号：US06841883B1
公开(公告)日：2005-01-11
申请号：US10403937
申请日：2003-03-31
申请人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
发明人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
IPC分类号： H01L21/56 , H01L21/60 , H01L21/768 , H01L21/98 , H01L23/31 , H01L23/48 , H01L25/065 , H01L29/40
CPC分类号： H01L21/561 , B33Y70/00 , B33Y80/00 , H01L21/563 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05111 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/05666 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/16145 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/351 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.
摘要翻译：半导体部件包括基模和层叠在基模上的二次模。基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板终端接触。一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

82. 发明授权

US06553276B2 Method of using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs 失效
标题翻译：集成电路（IC）使用数据的方法已经进行了修复，以选择IC将要进行的程序，例如额外修理
公开(公告)号：US06553276B2
公开(公告)日：2003-04-22
申请号：US10071961
申请日：2002-02-05
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F1900
CPC分类号： G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要翻译：一种集成电路（IC）制造过程中的发明方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修复，包括将数据与每个的保险丝ID相关联地存储 IC的。例如，在制造过程中，IC的ID代码将自动读取，例如打开/短路测试。然后访问与IC的ID代码相关联存储的数据，并且根据访问的数据选择IC可能经历的附加修复过程。因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

83. 发明授权

US06529027B1 Interposer and methods for fabricating same 失效
标题翻译：插件及其制造方法
公开(公告)号：US06529027B1
公开(公告)日：2003-03-04
申请号：US09533407
申请日：2000-03-23
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R3102
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，其包括接纳半导体器件（例如倒装芯片型半导体器件）与栅介质基板的栅栏。栅栏可以包括被配置为使半导体器件与插入器衬底逐渐对准的边缘。挡板还可以包括一个或多个侧向凹入区域，以便于半导体器件与插入器基板的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向应用于一层或多层以形成栅栏。结果，内插器基板不需要精确地机械对准。

84. 发明授权

US06465877B1 Semiconductor package including flex circuit, interconnects and dense array external contacts 有权
标题翻译：半导体封装包括柔性电路，互连和密集阵列外部触点
公开(公告)号：US06465877B1
公开(公告)日：2002-10-15
申请号：US09536827
申请日：2000-03-27
申请人： Warren M. Farnworth , Alan G. Wood , Mike Brooks
发明人： Warren M. Farnworth , Alan G. Wood , Mike Brooks
IPC分类号： H01L23495
CPC分类号： H01L23/49827 , H01L23/4985 , H01L2224/02333 , H01L2224/73215 , H01L2924/09701 , H01L2924/12044 , H01L2924/15173
摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.
摘要翻译：提供了一种芯片级半导体封装和一种制造该封装的方法。该封装包括半导体管芯和连接到管芯的表面的柔性电路。柔性电路包括具有密集阵列的外部触点的聚合物基板和与外部触点电连通的导体图案。封装还包括被配置为在管芯触头（例如，焊盘）之间提供分开的电路径的互连件以及柔性电路上的导体。提供了互连的几个不同实施例，包括：在裸片上的凸起接触，用导电粘合剂层结合到柔性电路导体上; 导体上的聚合物凸块或模具接触件以半固化状态施加，然后完全固化; 使用焊接工具彼此接合的管芯触点和导体上的焊料凸块; 使用金属凸块和引线接合或球焊接装置形成的导体和裸片接触之间的铆钉状接合连接; 导体和裸片接点之间的单点接合连接，用接合工具形成; 以及导体和裸片接触之间的引线键合。

85. 发明授权

US06414506B1 Interconnect for testing semiconductor dice having raised bond pads 有权
公开(公告)号：US06414506B1
公开(公告)日：2002-07-02
申请号：US09213573
申请日：1998-12-17
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： G01R3126
摘要： A method for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) and a method for forming an interconnect suitable for testing this type of dice are provided. The interconnect includes a substrate having contact members comprising an array of sharpened elongated projections. The sharpened projections are formed by etching (or by growing and removing an oxide) through exposed areas of a mask. A conductive layer is formed on the sharpened projections and is in electrical communication with conductive traces formed on the substrate. The conductive layer can be formed as a layer of metal, as a stack of metals including a barrier metal, as a silicide, or as a layer of polysilicon. For testing an unpackaged die, the interconnect and die are placed in a temporary carrier and biased together. The sharpened projections are adapted to penetrate the contact location on the die to a limited penetration depth to establish an ohmic connection while minimizing damage to the contact location.

86. 发明授权

US06383825B1 Method and system for testing semiconductor dice, semiconductor packages and semiconductor wafers 失效
标题翻译：用于测试半导体芯片，半导体封装和半导体晶圆的方法和系统
公开(公告)号：US06383825B1
公开(公告)日：2002-05-07
申请号：US09902396
申请日：2001-07-10
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2166
CPC分类号： H01L22/22 , H01L2224/48091 , H01L2924/00014
摘要： A method and system for making known good semiconductor dice are provided. The method includes providing a semiconductor die with programmable links, such as fuses or anti-fuses, that permit defects on the die to be corrected during a testing procedure. The system includes a testing apparatus in electrical communication with testing circuitry and with programming circuitry. During the testing procedure defects on the die can be detected and then corrected by selective actuation of the programmable links. Once the defects have been corrected the rehabilitated die can be retested and reburned-in, if necessary, for certification as a known good die. In an illustrative embodiment, the testing apparatus is adapted to electrically connect to multiple dice individually packaged in temporary packages. In an alternate embodiment, the testing apparatus comprises a board adapted to electrically connect to multiple unpackaged dice. In another alternate embodiment the testing apparatus comprises a board adapted to electrically connect to a semiconductor wafer comprising a plurality of dice.
摘要翻译：提供了制造已知的良好半导体晶片的方法和系统。该方法包括提供具有诸如保险丝或抗熔丝等可编程链路的半导体管芯，其允许在测试过程期间校正管芯上的缺陷。该系统包括与测试电路和编程电路进行电气通信的测试装置。在测试过程中，可以检测模具上的缺陷，然后通过可编程链路的选择性启动来校正缺陷。一旦缺陷得到纠正，修复后的模具就可以重新测试，如果需要，可以重新进行认证，作为一个已知的好死者。在说明性实施例中，测试装置适于电连接到单独封装在临时包装中的多个骰子。在替代实施例中，测试装置包括适于电连接到多个未封装的裸片的板。在另一替代实施例中，测试装置包括适于电连接到包括多个裸片的半导体晶片的板。

87. 发明授权

US06319354B1 System and method for dicing semiconductor components 失效
标题翻译：用于切割半导体部件的系统和方法
公开(公告)号：US06319354B1
公开(公告)日：2001-11-20
申请号：US09693443
申请日：2000-10-20
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： B32B3500
CPC分类号： H01L21/6835 , B28D5/0094 , H01L21/3043 , H01L21/481 , H01L21/6836 , H01L21/78 , H01L2221/68313 , H01L2221/68327 , H01L2224/4824 , H01L2924/01087 , H01L2924/10253 , H01L2924/15311 , Y10S156/941 , Y10S438/976 , Y10T156/11 , Y10T156/1132 , Y10T156/19 , Y10T156/1944 , H01L2924/00
摘要： A method and system for dicing semiconductor components, such as bare dice and chip scale packages, are provided. Initially, the semiconductor components are contained on a wafer or a panel. Next, an insert that includes a base and an adhesive layer, is used to support the substrate for separation into separate components by sawing or other process. The insert with the separated components retained thereon, is then transferred to a carrier tray constructed according to JEDEC standards. The carrier tray is adapted for stacking and for handling by conveyors, magazines and other standard equipment. The system includes the substrate, the insert, and the standardized carrier tray.
摘要翻译：提供了用于切割半导体部件的方法和系统，例如裸裸片和芯片级封装。最初，半导体元件被包含在晶片或面板上。接下来，包括基底和粘合剂层的插入物用于通过锯切或其它工艺来支撑基底以分离成单独的部件。然后将保留在其上的分离的部件的插入物转移到根据JEDEC标准构造的载体托盘。托盘适于堆放和由输送机，杂志和其他标准设备进行处理。该系统包括基板，插入件和标准化托盘。

88. 发明授权

US06296171B1 Utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems 失效
标题翻译：利用超声波能量来减少已知好的模具或永久接触系统中的初始接触力
公开(公告)号：US06296171B1
公开(公告)日：2001-10-02
申请号：US09416248
申请日：1999-10-12
申请人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
发明人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
IPC分类号： B23K106
CPC分类号： B23K20/10 , B23K2101/38
摘要： A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
摘要翻译：用于将互连的穿刺型导电接触构件接合到裸半导体管芯的接合焊盘的机器和方法包括使用安装成振动模具和互连中的一个或两者的一个或两个超声波振动器。超声能量的短轴向线性爆发使得接触构件能够以低得多的压缩力在接合焊盘的表面上刺穿硬氧化物层并且迅速地实现完全的穿透深度。

89. 发明授权

US06258609B1 Method and system for making known good semiconductor dice 失效
标题翻译：制造已知的良好半导体晶片的方法和系统
公开(公告)号：US06258609B1
公开(公告)日：2001-07-10
申请号：US08719850
申请日：1996-09-30
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2166
CPC分类号： H01L22/22 , H01L2224/48091 , H01L2924/00014
摘要： A method and system for making known good semiconductor dice are provided. The method includes providing a semiconductor die with programmable links, such as fuses or anti-fuses, that permit defects on the die to be corrected during a testing procedure. The system includes a testing apparatus in electrical communication with testing circuitry and with programming circuitry. During the testing procedure defects on the die can be detected and then corrected by selective actuation of the programmable links. Once the defects have been corrected the rehabilitated die can be retested and reburned-in, if necessary, for certification as a known good die. In an illustrative embodiment, the testing apparatus is adapted to electrically connect to multiple dice individually packaged in temporary packages. In an alternate embodiment, the testing apparatus comprises a board adapted to electrically connect to multiple unpackaged dice. In another alternate embodiment the testing apparatus comprises a board adapted to electrically connect to a semiconductor wafer comprising a plurality of dice.
摘要翻译：提供了制造已知的良好半导体晶片的方法和系统。该方法包括提供具有诸如保险丝或抗熔丝等可编程链路的半导体管芯，其允许在测试过程期间校正管芯上的缺陷。该系统包括与测试电路和编程电路进行电气通信的测试装置。在测试过程中，可以检测模具上的缺陷，然后通过可编程链路的选择性启动来校正缺陷。一旦缺陷得到纠正，修复后的模具就可以重新测试，如果需要，可以重新进行认证，作为一个已知的好死者。在说明性实施例中，测试装置适于电连接到单独封装在临时包装中的多个骰子。在替代实施例中，测试装置包括适于电连接到多个未封装的裸片的板。在另一替代实施例中，测试装置包括适于电连接到包括多个裸片的半导体晶片的板。

90. 发明授权

US06208157B1 Method for testing semiconductor components 有权
标题翻译：半导体元件测试方法
公开(公告)号：US06208157B1
公开(公告)日：2001-03-27
申请号：US09298769
申请日：1999-04-23
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

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