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81. 发明授权

US5402383A Electrically erasable non-volatile semiconductor memory device for selective use in boot block type or normal type flash memory devices 失效
标题翻译：电可擦除非易失性半导体存储器件，用于引导块型或正常型闪存器件中的选择性使用
公开(公告)号：US5402383A
公开(公告)日：1995-03-28
申请号：US078818
申请日：1993-06-21
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G06F12/00 , G11C16/02 , G11C16/12 , G11C16/16 , G11C17/00 , G11C13/00
CPC分类号： G11C16/16 , G11C16/12
摘要： An electrically erasable non-volatile semiconductor memory device has a memory cell array, a first erase unit, a second erase unit, and an operation mode establish unit. The erasing operation of the second erase unit is independently carried out of the erasing operation of the first erase unit. When a first operation mode is established by the operation mode establish unit, the second erase unit is inactivated, and the erasing operation of the memory cell array is only carried out by the first erase unit. On the other hand, when a second operation mode is established by the operation mode establish unit, the erasing operation of the first erase unit for a part of the memory cell array is disable, and the second erase unit is activated and the erasing operation for the part of the memory cell array is carried out by the second erase unit. Therefore, the change between a boot block type flash memory and normal type flash memory can be realized only by changing an establish value of the operation mode establish unit. Consequently, when developing both boot block type flash memory and normal type flash memory, these two types of flash memories can be obtained by using the same chip or by carrying out only minimum changes, so that the developing processes can be greatly decreased.
摘要翻译：电可擦除非易失性半导体存储器件具有存储单元阵列，第一擦除单元，第二擦除单元和操作模式建立单元。第二擦除单元的擦除操作独立地执行第一擦除单元的擦除操作。当由操作模式建立单元建立第一操作模式时，第二擦除单元被禁用，并且存储单元阵列的擦除操作仅由第一擦除单元执行。另一方面，当通过操作模式建立单元建立第二操作模式时，对于存储单元阵列的一部分的第一擦除单元的擦除操作被禁用，并且第二擦除单元被激活，并且擦除操作存储单元阵列的一部分由第二擦除单元执行。因此，仅通过改变操作模式建立单元的建立值才能实现引导块型闪速存储器与正常型闪速存储器之间的变化。因此，当开发引导块型闪速存储器和普通型闪速存储器时，可以通过使用相同的芯片或仅通过执行最小变化来获得这两种类型的闪存，从而可以大大降低显影过程。

82. 发明授权

US5280451A Signature circuit for non-volatile memory device 失效
标题翻译：用于非易失性存储器件的签名电路
公开(公告)号：US5280451A
公开(公告)日：1994-01-18
申请号：US656501
申请日：1991-02-19
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C17/00 , G11C5/00 , G11C16/20 , G11C29/00
CPC分类号： G11C16/20 , G11C5/00
摘要： A signature circuit stores signature information indicative of one of a plurality of device functions of a non-volatile memory device which includes first memory cells which are respectively coupled to one of a plurality of word lines and to one of a plurality of bit lines. The signature circuit includes second memory cells which are respectively connected to the bit lines which are grouped into a plurality of blocks, at least one predetermined word line which is provided exclusively for the second memory cells and is connected to each of the memory cells, and a selecting circuit coupled to the bit lines for selecting one of the blocks. The second memory cells in each of the blocks store one kind of signature information, so that a number of blocks is equal to a number of kinds of signature information that can be stored in the signature circuit.
摘要翻译：签名电路存储指示非易失性存储器件的多个器件功能之一的签名信息，该非易失性存储器件包括分别耦合到多条字线之一和多条位线之一的第一存储器单元。签名电路包括分别连接到分组为多个块的位线的第二存储器单元，专门为第二存储单元提供并连接到每个存储器单元的至少一个预定字线，以及耦合到所述位线的选择电路，用于选择所述块中的一个。每个块中的第二存储单元存储一种签名信息，使得多个块等于可以存储在签名电路中的签名信息的种类数量。

83. 发明授权

US5038327A Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors 失效
标题翻译：可擦写可编程只读存储器的解码电路，用于避免由寄生电容引起的错误操作
公开(公告)号：US5038327A
公开(公告)日：1991-08-06
申请号：US584956
申请日：1990-09-18
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C17/00 , G11C8/10 , G11C11/408 , G11C11/413 , G11C16/08 , G11C17/18 , H03K19/003
CPC分类号： H03K19/00361 , G11C16/08 , G11C17/18 , G11C8/10
摘要： A load unit is connected between a high potential power supply line and a decoded output terminal, a plurality of decoder transistors are connected in series between the decoded output terminal and a low potential power supply line, and gates of the decoder transistors are supplied with input signals. A current supply unit is connected to at least one of a plurality of connection points of the decoder transistors, so that capacitors parasitically formed at the connection points of the decoder transistors are not only charged by a current from the load unit, but also charged by a current from a current from the current supply unit. Therefore, an erroneous operation of the decoder circuit caused by the parasitic capacitors can be avoided without increasing the access time and power consumption thereof.

84. 发明授权

US4998223A Programmable semiconductor memory apparatus 失效
标题翻译：可编程半导体存储器件
公开(公告)号：US4998223A
公开(公告)日：1991-03-05
申请号：US550786
申请日：1990-07-10
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C17/00 , G06F11/00 , G11C5/00 , G11C16/08 , G11C16/20 , G11C16/24 , G11C29/00 , G11C29/12
CPC分类号： G11C5/00 , G06F11/006 , G11C16/08 , G11C16/20 , G11C16/24
摘要： A programmable semiconductor memory apparatus comprises a memory cell array, a data sense circuit for reading data from the memory cell array, and a bus line connected to a common node of a plurality of bit lines forming the memory cell array and to the data sense circuit, a circuit for storing an identifying code for identifying the programmable semiconductor memory apparatus is connected to the bus line, thereby enabling the identifying code to be read externally.

85. 发明申请

US20120057406A1 FLASH MEMORY APPARATUS 审中-公开
标题翻译：闪存设备
公开(公告)号：US20120057406A1
公开(公告)日：2012-03-08
申请号：US12874491
申请日：2010-09-02
申请人： TAKAO AKAOGI
发明人： TAKAO AKAOGI
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C16/0483
摘要： A flash memory apparatus includes a plurality of memory sectors and a plurality of path transistors, and each memory sector has a local low voltage line, and each path transistor corresponds to one of the memory sectors, and the path transistors are installed in an alignment direction of the memory sectors. One of the path transistors is installed between two adjacent memory sectors, whose gate is connected to a sector select signal line, and whose drain is connected to the local low voltage line of the corresponding memory sector, and whose source is connected to a global low voltage line, and the global low voltage line is installed at an angle substantially equal to 90 degrees across the gate, so as to save the area occupied by peripheral circuits in the path transistors, and lower the manufacturing cost of the flash memory apparatus.
摘要翻译：闪速存储装置包括多个存储器扇区和多个路径晶体管，并且每个存储器扇区具有局部低电压线，并且每个路径晶体管对应于存储器扇区中的一个，并且路径晶体管以对准方向的内存扇区。路径晶体管中的一个安装在两个相邻的存储器扇区之间，其两个栅极连接到扇区选择信号线，其漏极连接到相应存储器扇区的局部低电压线，其源极连接到全局低电平电压线，并且全局低电压线以跨过门的大致等于90度的角度安装，以便将外围电路占据的面积保存在路径晶体管中，并降低闪存装置的制造成本。

86. 发明申请

US20100238731A1 PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL 有权
标题翻译：记忆体通道的局部自动升压
公开(公告)号：US20100238731A1
公开(公告)日：2010-09-23
申请号：US12407228
申请日：2009-03-19
申请人： Youseok Suh , Ya-Fen Lin , Colin Stewart Bill , Takao Akaogi , Yi-Ching Wu
发明人： Youseok Suh , Ya-Fen Lin , Colin Stewart Bill , Takao Akaogi , Yi-Ching Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.
摘要翻译：公开了一种用于存储器单元通道的局部局部自升压的方法。作为存储单元通道部分局部自升压的一部分，位于程序禁止存储单元的源极侧的隔离存储单元被截止，并且位于程序禁止存储单元的漏极侧的门控存储单元被用于将预充电电压传递到程序禁止的存储单元，以向编程禁止的存储单元的通道提供预充电电压。此外，预充电电压被传递到位于程序禁止的存储单元的源极侧的缓冲存储单元，以向缓冲存储单元的通道和位于该存储单元上的选通存储单元提供预充电电压程序的漏极侧禁止存储单元关闭。在编程期间，将程序禁止存储单元的通道电压升高到由预充电电压升高的电平以上的程序禁止存储单元的栅极上施加编程电压。

87. 发明授权

US07498849B2 Sense amplifiers with high voltage swing 有权
标题翻译：具有高电压摆幅的感应放大器
公开(公告)号：US07498849B2
公开(公告)日：2009-03-03
申请号：US11985427
申请日：2007-11-15
申请人： Takao Akaogi , Sameer Wadhwa , Michael Achter , Bhimachar Venkatesh
发明人： Takao Akaogi , Sameer Wadhwa , Michael Achter , Bhimachar Venkatesh
IPC分类号： G01R19/00 , G11C7/00
CPC分类号： G11C7/062 , G11C2207/063 , H03F3/345 , H03F3/45183 , H03F3/45475 , H03F2200/462 , H03F2200/78
摘要： A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.
摘要翻译：读出放大器包括用于产生参考输出电压的参考电压发生器和用于产生核心输出电压的核心输出电压发生器。核心输出电压发生器包括核心前端级和核心后端级，或者包括多个放大器晶体管，每个放大器晶体管通过诸如核心单元之类的电流传导器件导通核心电流的一部分。这种组件的晶体管的尺寸和/或连接导致高电压摆动，从而导致读出放大器的高灵敏度。

88. 发明授权

US07283398B1 Method for minimizing false detection of states in flash memory devices 有权
标题翻译：用于最小化闪速存储器件中的状态的错误检测的方法
公开(公告)号：US07283398B1
公开(公告)日：2007-10-16
申请号：US10838962
申请日：2004-05-04
申请人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
发明人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
摘要翻译：本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。多个字线被布置成多行。多个位线被布置在多个列中。该方法通过确定与一列存储器单元相关联的所选位线开始。然后，该方法通过在一个负电压下偏置一组字线来继续。字线组电耦合到相关联的存储器单元。当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。

89. 发明申请

US20070002602A1 Power interconnect structure for balanced bitline capacitance in a memory array 有权
公开(公告)号：US20070002602A1
公开(公告)日：2007-01-04
申请号：US11173930
申请日：2005-07-01
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C5/06
CPC分类号： H01L23/5286 , H01L23/5222 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure situated over the memory core array, where the interconnect structure is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines. The interconnect structure can include at least one interconnect line, which can form an angle with respect to the bitlines that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure can form one of a number of capacitances with each of the bitlines, where each of the capacitances can be substantially equal in value to each other of the capacitances.

90. 发明授权

US07126862B2 Decoder for memory device 有权
公开(公告)号：US07126862B2
公开(公告)日：2006-10-24
申请号：US11076252
申请日：2005-03-08
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C16/06 , G11C16/08 , G11C11/24 , G11C8/00 , G11C8/08 , G11C8/10
CPC分类号： G11C16/08 , G11C8/08
摘要： A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls the driving devices to turn on or off. Also, a capacitor coupled to the common node increases the voltage at the common node from an initial boost voltage to a final boost voltage. Thus, a line of a memory device is driven to a boost voltage with minimized area and wiring complexity.

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