专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20090319719A1 System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices 审中-公开
标题翻译：具有控制器装置，缓冲器装置和多种存储器件的系统
公开(公告)号：US20090319719A1
公开(公告)日：2009-12-24
申请号：US12411003
申请日：2009-03-25
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/06
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.
摘要翻译：一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。第一多个信号线耦合到控制器设备。第二多个信号线耦合到第一存储器件和集成电路缓冲器件。第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。第三组信号线耦合到第一存储器件和集成电路缓冲器件。第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。第一信号线耦合到第一存储器件和集成电路缓冲器件。第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。

82. 发明授权

US07577789B2 Upgradable memory system with reconfigurable interconnect 有权
标题翻译：具有可重构互连的可升级内存系统
公开(公告)号：US07577789B2
公开(公告)日：2009-08-18
申请号：US11388449
申请日：2006-03-24
申请人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00 , G06F12/04
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
摘要翻译：描述的是采用可配置的片上终端元件的系统，其允许用户从两个或多个端接拓扑中进行选择。一个拓扑结构可编程，以支持轨到轨或半电源终端。另一种拓扑选择性地包括固定或可变滤波器元件，从而允许针对不同级别的速度性能和功耗来调整终端特性。终端电压和阻抗也可能会被调整。

83. 发明申请

US20090138646A1 METHOD AND APPARATUS FOR SIGNALING BETWEEN DEVICES OF A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统的设备之间进行信号的方法和装置
公开(公告)号：US20090138646A1
公开(公告)日：2009-05-28
申请号：US12360780
申请日：2009-01-27
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/28
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.
摘要翻译：提供了一种用于在存储器系统的设备之间进行信令的方法和装置。根据本发明的实施例，实现了几个能力中的一个或多个，以提供迄今为止无法达到的重要系统度量的水平，例如高性能和/或低成本。这些功能涉及定时调整能力，位时间调整能力，周期时间选择，对总线信号和/或时钟信号的差分和/或非差分信号的使用，以及在总线上使用终端结构，包括集成终端结构，以及主动控制电路，允许调整不同的特性总线阻抗和功率状态控制，包括优化终端值的校准过程，使用压摆率控制电路和传输特征控制电路在发射机模块的预驱动器和驱动器中，以允许调整不同的特性总线阻抗，并允许调整其他总线属性，包括优化这种电路的校准过程，和/或提供被设计为预先获取（预访问）字的存储器组件，其宽于数据总线的宽度，使得存储器访问带宽近似匹配传输带宽和备忘录 ry组件能够调整预取（预访问）字的大小，以适应与不同宽度的数据总线的连接。

84. 发明申请

US20090063887A1 MEMORY MODULE WITH TERMINATION COMPONENT 有权
标题翻译：具有终止组件的存储模块
公开(公告)号：US20090063887A1
公开(公告)日：2009-03-05
申请号：US12111816
申请日：2008-04-29
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F1/08
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
摘要翻译：一种具有第一和第二接口的存储器组件。提供第一接口以响应于第一时钟信号对地址信息进行采样。第一接口包括在第一时钟信号的时钟周期期间连续地采样地址信息的至少两个比特的输入。提供第二接口以响应于第二时钟信号采样数据，其具有至少是第一时钟信号频率的两倍的频率。第二接口包括在第二时钟信号的时钟周期期间连续采样至少两位数据的输入。

85. 发明授权

US07484064B2 Method and apparatus for signaling between devices of a memory system 有权
标题翻译：用于在存储器系统的设备之间进行信令的方法和装置
公开(公告)号：US07484064B2
公开(公告)日：2009-01-27
申请号：US10053340
申请日：2001-10-22
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.
摘要翻译：提供了一种用于在存储器系统的设备之间进行信令的方法和装置。根据本发明的实施例，实现了几个能力中的一个或多个，以提供迄今为止无法达到的重要系统度量的水平，例如高性能和/或低成本。这些功能涉及定时调整能力，位时间调整能力，周期时间选择，对总线信号和/或时钟信号的差分和/或非差分信号的使用，以及在总线上使用终端结构，包括集成终端结构，以及主动控制电路，允许调整不同的特性总线阻抗和功率状态控制，包括优化终端值的校准过程，使用压摆率控制电路和传输特征控制电路在发射机模块的预驱动器和驱动器中，以允许调整不同的特性总线阻抗，并允许调整其他总线属性，包括优化这种电路的校准过程，和/或提供被设计为预先获取（预访问）字的存储器组件，其宽于数据总线的宽度，使得存储器访问带宽近似匹配传输带宽和备忘录 ry组件能够调整预取（预访问）字的大小，以适应与不同宽度的数据总线的连接。

86. 发明申请

US20080209141A1 Memory System And Device With Serialized Data Transfer 有权
标题翻译：具有序列化数据传输的存储器系统和器件
公开(公告)号：US20080209141A1
公开(公告)日：2008-08-28
申请号：US12116439
申请日：2008-05-07
申请人： Richard E. Perego , Fredrick A. Ware
发明人： Richard E. Perego , Fredrick A. Ware
IPC分类号： G06F12/00
CPC分类号： G06F13/1684
摘要： A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
摘要翻译：具有序列化数据传输的存储系统。存储器系统包括在存储器控制器和多个存储器件内。存储器控制器从主机接收多个写入数据值，并将写入数据值作为相应串行比特流输出。每个存储器件从存储器控制器接收至少一个串行比特流，并将串行比特流转换为一组并行比特以进行存储。

87. 发明授权

US07380092B2 Memory device and system having a variable depth write buffer and preload method 有权
标题翻译：具有可变深度写入缓冲器和预加载方法的存储器件和系统
公开(公告)号：US07380092B2
公开(公告)日：2008-05-27
申请号：US10442352
申请日：2003-05-21
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F13/00
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C2207/2281 , G11C2207/229
摘要： A variable depth write data buffer is provided in a memory device coupled to a master device by an interconnect structure in an embodiment of the present invention. The variable depth write data buffer reduces a delay, or W-R turnaround bubble, time between a read operation and a write operation of a memory device memory core. The variable depth write buffer is programmable to store 1 to 4 data packets in an embodiment of the present invention. The variable depth write data buffer may also be programmed for multiple memory device configurations. A method preloads write data without address information into a write data buffer and a subsequent WRITE command causes the previously loaded write data to be retrieved from the write data buffer and written to a memory core according to an embodiment of the present invention.
摘要翻译：在本发明的实施例中，通过互连结构在连接到主设备的存储器件中提供可变深度写入数据缓冲器。可变深度写入数据缓冲器减少了存储器件存储器核心的读取操作和写入操作之间的延迟或W-R周转气泡。在本发明的实施例中，可变深度写入缓冲器是可编程的，以存储1到4个数据分组。可变深度写入数据缓冲器也可以被编程用于多个存储器件配置。一种方法将没有地址信息的写数据预加载到写数据缓冲器中，并且随后的写命令使根据本发明实施例的从写数据缓冲器检索先前加载的写数据并将其写入存储器核。

88. 发明授权

US07206896B2 Integrated circuit buffer device 失效
标题翻译：集成电路缓冲器
公开(公告)号：US07206896B2
公开(公告)日：2007-04-17
申请号：US11119031
申请日：2005-04-29
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： An integrated circuit buffer device comprises a first receiver circuit to receive control information and address information from a controller device. A first interface includes a first interface portion to provide a first address to a first memory device. A second interface portion provides a first control signal to the first memory device. The first control signal specifies a read operation such that the first memory device provides a first data, accessed from a memory location based on the first address, to the integrated circuit buffer device in response to the first control signal specifying the read operation. A third interface portion provides a first clock signal to the first memory device. The first clock signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion receives the first data. A second interface includes a first interface portion to provide a second address to a second memory device. A second interface portion provides a second control signal to the second memory device. A third interface portion provides a second clock signal to the second memory device. A fourth interface portion receives the second data. A first transmitter circuit transmits the first read data and the second read data to the controller device.
摘要翻译：集成电路缓冲器件包括用于从控制器装置接收控制信息和地址信息的第一接收器电路。第一接口包括向第一存储器件提供第一地址的第一接口部分。第二接口部分向第一存储器件提供第一控制信号。第一控制信号指定读操作，使得第一存储器件响应于指定读操作的第一控制信号，将从第一地址的存储器位置访问的第一数据提供给集成电路缓冲器件。第三接口部分向第一存储器件提供第一时钟信号。第一时钟信号使来自集成电路缓冲器的第一控制信号与第一存储器件的通信同步。第四接口部分接收第一数据。第二接口包括向第二存储器设备提供第二地址的第一接口部分。第二接口部分向第二存储器件提供第二控制信号。第三接口部分向第二存储器件提供第二时钟信号。第四接口部分接收第二数据。第一发送器电路将第一读取数据和第二读取数据发送到控制器装置。

89. 发明授权

US07200055B2 Memory module with termination component 有权
标题翻译：具有终端组件的内存模块
公开(公告)号：US07200055B2
公开(公告)日：2007-04-03
申请号：US11219381
申请日：2005-09-01
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having a termination component. The memory module includes first and second memory devices, a termination component and three sets of signal lines. A first set of signal lines is coupled to the first memory device and dedicated to data transfers involving the first memory device. A second signal lines is coupled to the second memory device and dedicated to data transfers involving the second memory device. A third set of signal lines is coupled to the first and second memory devices and the termination component such that a signal propagating on the third set of signal lines propagates past the first memory device before reaching the second memory device, and propagates past the second memory device before reaching the termination component.
摘要翻译：一种具有端接部件的存储器模块。存储器模块包括第一和第二存储器件，终端元件和三组信号线。第一组信号线耦合到第一存储器设备，并专用于涉及第一存储器件的数据传输。第二信号线耦合到第二存储器设备，并专用于涉及第二存储器件的数据传输。第三组信号线耦合到第一和第二存储器件和端接部件，使得在第三组信号线传播的信号在到达第二存储器件之前传播通过第一存储器件，并且传播通过第二存储器设备到达终端组件之前。

90. 发明授权

US07177998B2 Method, system and memory controller utilizing adjustable read data delay settings 有权
标题翻译：方法，系统和存储器控制器利用可调读数据延迟设置
公开(公告)号：US07177998B2
公开(公告)日：2007-02-13
申请号：US11335029
申请日：2006-01-18
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/20
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.
摘要翻译：使用可调读数据延迟设置的方法，系统和内存控制器。存储器控制器包括控制发射电路，数据接收电路和定时电路。控制电路通过共享控制信号路径将控制信号发送到多个存储器件。数据接收电路经由相应的数据信号路径从存储器件接收数据信号。定时电路延迟每个数据信号路径上的数据信号的接收相应的时间间隔，该时间间隔至少部分地基于控制信号在从存储器控制器到控制信号路径的传播所需的时间相应的一个存储器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式