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81. 发明授权

US07710817B2 Semiconductor memory device having a delay locked loop (DLL) and method for driving the same 有权
标题翻译：具有延迟锁定环（DLL）的半导体存储器件及其驱动方法
公开(公告)号：US07710817B2
公开(公告)日：2010-05-04
申请号：US11819803
申请日：2007-06-29
申请人： Kyoung-Nam Kim , Yoon-Jae Shin
发明人： Kyoung-Nam Kim , Yoon-Jae Shin
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/02 , G11C7/222
摘要： A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal.
摘要翻译：半导体存储器件包括：调制控制器，用于产生用于控制频率调制操作的调制控制信号; 延迟锁定环（DLL）电路，用于执行延迟锁定操作以产生第一和第二DLL时钟并响应于调制控制信号输出调频DLL时钟; 以及数据选通信号发生器，用于输出调频DLL时钟作为数据选通信号。

82. 发明授权

US07612591B2 DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus 有权
标题翻译：半导体存储装置的DLL电路以及延迟和锁定半导体存储装置中的时钟的方法
公开(公告)号：US07612591B2
公开(公告)日：2009-11-03
申请号：US12185835
申请日：2008-08-05
申请人： Kyoung Nam Kim
发明人： Kyoung Nam Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03L7/091
摘要： A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.
摘要翻译：半导体存储装置的DLL电路包括频率感测单元，其基于CAS等待时间信号生成并输出高频信号和低频信号。时钟分频单元将内部时钟的频率除以预定值，并且响应于高频信号是使能还是使能低频信号而产生分频时钟。切换参考时钟和比较时钟的相位感测单元根据高频信号是使能还是使能低频信号进行比较，选择性地切换基于该时钟生成的第一和第二相位控制信号比较结果，并输出开关信号。

83. 发明授权

US07573308B2 Delay locked loop circuit for preventing malfunction caused by change of power supply voltage 有权
标题翻译：延迟锁定环电路，用于防止由电源电压变化引起的故障
公开(公告)号：US07573308B2
公开(公告)日：2009-08-11
申请号：US11647219
申请日：2006-12-29
申请人： Kyoung-Nam Kim
发明人： Kyoung-Nam Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0814
摘要： A Delay Locked Loop (DLL) circuit prevents a malfunction caused by a change of a power supply voltage, and includes a first and a second delay lines and a first and a second signal processors for controlling the first and the second delay lines, and turns off the second signal processor after DLL locking. The DLL circuit further includes a phase comparator for generating a comparison signal notifying which of phases of a first clock signal of the first delay line and a second clock signal of the second delay line precedes the other, and a signal selector for inputting an output of the second signal processor to the second delay line before the DLL locking, and inputting the comparison signal of the phase comparator to the second delay line after the DLL locking.
摘要翻译：延迟锁定回路（DLL）电路防止由电源电压变化引起的故障，并且包括第一和第二延迟线以及用于控制第一和第二延迟线的第一和第二信号处理器，并且转动关闭第二个信号处理器后DLL锁定。 DLL电路还包括相位比较器，用于产生比较信号，该比较信号通知第一延迟线的第一时钟信号的相位和第二延迟线的第二时钟信号的哪一个相位在另一个之前的相位;以及信号选择器，用于输入第二信号处理器在DLL锁定之前到第二延迟线，并且在DLL锁定之后将相位比较器的比较信号输入到第二延迟线。

84. 发明申请

US20080309340A1 MAGNETIC RESONANCE IMAGING SYSTEM 有权
标题翻译：磁共振成像系统
公开(公告)号：US20080309340A1
公开(公告)日：2008-12-18
申请号：US12046209
申请日：2008-03-11
申请人： Zang Hee Cho , Young Bo Kim , Kyoung Nam Kim , Suk Min Hong
发明人： Zang Hee Cho , Young Bo Kim , Kyoung Nam Kim , Suk Min Hong
IPC分类号： G01R33/32
CPC分类号： G01R33/34046 , G01R33/34069 , G01R33/3415
摘要： A magnetic resonance imaging system is provided, which can provide the homogeneous magnetic field to obtain a head anatomic image with a high resolution and high SNR by coaxially disposing a receive-only phased array antenna inside a transmit-only antenna with a predetermined gap, and thereby a detailed and accurate image of a man's head can be obtained. In the present invention, the system comprises: a transmit-only antenna comprising at least two saddle quadrature antennas connected with each other to form a ring shape, one of the connections being a joint and the remaining connections being formed in an overlapping fashion; and a receive-only phased array antenna comprising a plurality of receive-only antennas connected with each other to form a ring shape, one of the connections being a joint and the remaining connections being formed in an overlapping fashion, wherein an inner diameter of the receive-only phased array antenna is shorter than that of the transmit-only antenna, and the receive-only phased array antenna is coaxially disposed inside the transmit-only antenna with a predetermined gap.
摘要翻译：提供一种磁共振成像系统，其可以提供均匀的磁场以通过在仅具有预定间隙的仅发射天线内同轴地布置仅接收相位阵列天线来获得具有高分辨率和高SNR的头部解剖图像，以及从而可以获得人的头部的详细和准确的图像。在本发明中，该系统包括：包括至少两个彼此连接的鞍形正交天线以形成环形的仅发射天线，其中一个连接是接头，其余连接以重叠的方式形成; 以及接收相位阵列天线，其包括彼此连接以形成环形的多个仅接收天线，所述连接中的一个是接头，并且所述剩余连接以重叠的方式形成，其中，只接收相位阵列天线短于仅发射天线的天线，并且仅接收相位阵列天线以预定间隙同轴地布置在仅发射天线内。

85. 发明申请

US20080285373A1 ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS 有权
标题翻译：地址接收电路用于半导体器件
公开(公告)号：US20080285373A1
公开(公告)日：2008-11-20
申请号：US11961963
申请日：2007-12-20
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

86. 发明授权

US07450440B2 Circuit for initializing a pipe latch unit in a semiconductor memory device 有权
标题翻译：用于在半导体存储器件中初始化管道锁存单元的电路
公开(公告)号：US07450440B2
公开(公告)日：2008-11-11
申请号：US11478123
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/1039
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.
摘要翻译：一种半导体存储器件包括具有用于锁存数据的多个管道锁存器的管道锁存单元。输入控制器控制从数据线发送到管道锁存单元的数据的输入定时。输出控制器控制锁存在管道锁存单元中的数据的输出定时。初始化控制器控制输入控制器和输出控制器，从而响应于在写操作期间被激活的读/写标志信号来初始化管锁存单元。

87. 发明授权

US07449498B2 Composite materials for bone defect filling and bone replacement 有权
标题翻译：用于骨缺损填充和骨置换的复合材料
公开(公告)号：US07449498B2
公开(公告)日：2008-11-11
申请号：US11296944
申请日：2005-12-08
申请人： Kyeong-Jun Park , Doug-Youn Lee , Sang-Bae Lee , Jeong-Jong Park , Ji-Ho Park , Kyoung-Nam Kim , Kwang-Mahn Kim
发明人： Kyeong-Jun Park , Doug-Youn Lee , Sang-Bae Lee , Jeong-Jong Park , Ji-Ho Park , Kyoung-Nam Kim , Kwang-Mahn Kim
IPC分类号： A61F2/28 , C08K9/04 , C08K3/32
CPC分类号： A61L24/0063 , A61L2430/02 , C08L35/04
摘要： The present invention relates to composite materials for bone replacement comprising organic and inorganic material, more particularly to composite materials for bone replacement wherein cyanoacrylate as organic material and osteo-conductive inorganic material as inorganic material are combined. The composite materials synthesized according to the present invention, maximize the merits of organic material and inorganic material and minimize their demerits. In detail, the organic material has the maintenance of shape and the adhesive property and the inorganic material has the osteo-conductivity on a new bone. Therefore, the composite materials of the present invention can be applied to fill bone defects and replace bones, since they retain the excellent physical property.
摘要翻译：本发明涉及用于骨替代的复合材料，其包括有机和无机材料，更具体地涉及用于骨替代的复合材料，其中将作为有机材料的氰基丙烯酸酯和作为无机材料的导电无机材料组合。根据本发明合成的复合材料使有机材料和无机材料的优点最大化并使其缺点最小化。详细地说，有机材料具有形状和粘合性的维持，并且无机材料在新骨上具有骨导电性。因此，本发明的复合材料可以应用于填充骨缺损和替代骨骼，因为它们保持优异的物理性能。

88. 发明申请

US20080240327A1 Semiconductor memory device capable of controlling tAC timing and method for operating the same 失效
标题翻译：能够控制tAC定时的半导体存储器件及其操作方法
公开(公告)号：US20080240327A1
公开(公告)日：2008-10-02
申请号：US12003549
申请日：2007-12-28
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： H03D3/24
CPC分类号： G11C16/32 , H03L7/0812
摘要： A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The delay locked loop circuit produces delay locked clock signals through a delay locking operation. The tAC control unit adjusts a delay value of the delay locked clock signals in order to control a tAC timing, thereby generating output reference signals. The reference signal generating unit produces a latch reference signal in response to the delay locked clock signals. The data output block latches data in response to the latch reference signal and for outputting the latched data in response to the output reference signals.
摘要翻译：半导体存储器件能够在输出数据处理中以定时裕度来控制tAC。半导体存储器件包括延迟锁定环电路，tAC控制单元，参考信号生成单元和数据输出块。延迟锁定环电路通过延迟锁定操作产生延迟锁定时钟信号。 tAC控制单元调整延迟锁定时钟信号的延迟值，以便控制tAC定时，从而产生输出参考信号。参考信号产生单元响应于延迟锁定时钟信号产生锁存参考信号。数据输出块根据锁存参考信号锁存数据，并根据输出参考信号输出锁存数据。

89. 发明申请

US20080211553A1 Delay locked loop in semiconductor memory device and method for generating divided clock therein 失效
公开(公告)号：US20080211553A1
公开(公告)日：2008-09-04
申请号：US12078095
申请日：2008-03-27
申请人： Kyoung-Nam Kim , Tae-Yun Kim
发明人： Kyoung-Nam Kim , Tae-Yun Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222
摘要： Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.

90. 发明申请

US20080205186A1 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080205186A1
公开(公告)日：2008-08-28
申请号：US11987832
申请日：2007-12-05
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/06 , G11C8/10
CPC分类号： G11C8/06 , G11C7/22 , G11C7/222
摘要： A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked loop (DLL) circuit from an outside to generate a reset signal for a reset operation of the DLL circuit in response to the normal register control signal or the extended register control signal; and the DLL circuit configured to perform a reset operation in response to the reset signal
摘要翻译：半导体存储器件包括：脉冲信号发生器，被配置为组合多个外部命令信号以响应于时钟信号产生正常寄存器控制信号和扩展寄存器控制信号; 复位信号发生器，被配置为响应于所述正常寄存器控制信号或所述扩展寄存器控制信号，从外部接收延迟锁定环路（DLL）电路的操作信息以产生用于所述DLL电路的复位操作的复位信号; 以及DLL电路，被配置为响应于复位信号执行复位操作

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