专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20070066083A1 Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same 有权
标题翻译：通过原子层沉积工艺形成富硅纳米晶体结构的方法和使用其制造非易失性半导体器件的方法
公开(公告)号：US20070066083A1
公开(公告)日：2007-03-22
申请号：US11494451
申请日：2006-07-28
申请人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
发明人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
IPC分类号： H01L21/31 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/02164 , B82Y10/00 , C23C16/308 , C23C16/401 , C23C16/45529 , H01L21/0214 , H01L21/02211 , H01L21/0228 , H01L21/02337 , H01L21/28273 , H01L21/3141 , H01L21/32055 , H01L29/42328 , Y10S438/962
摘要： In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.
摘要翻译：在通过ALD工艺形成富含硅的纳米晶体结构的方法中，将包含第一硅化合物的第一气体提供到物体上以在物体上形成富含硅的化学吸附层。在富含硅的化学吸附层上提供包含氧的第二气体，以在物体上形成富含硅的绝缘层。在富硅绝缘层上提供包括第二硅化合物的第三气体，以在富硅绝缘层上形成硅纳米晶层。可以重复地提供第一气体，第二气体和第三气体以交替地形成在物体上具有多个富硅绝缘层和多个硅纳米晶层的富含硅的纳米晶体结构。

82. 发明申请

US20060246661A1 Method of forming a thin layer and method of manufacturing a non-volatile semiconductor device using the same 失效
公开(公告)号：US20060246661A1
公开(公告)日：2006-11-02
申请号：US11398217
申请日：2006-04-05
申请人： Kyong-Hee Joo , Yong-Won Cha , Seung-Hyun Lim , In-Seok Yeo , Kyu-Tae Na
发明人： Kyong-Hee Joo , Yong-Won Cha , Seung-Hyun Lim , In-Seok Yeo , Kyu-Tae Na
IPC分类号： H01L21/336
CPC分类号： C23C16/042 , C23C16/507 , C23C16/56 , H01L21/0214 , H01L21/02164 , H01L21/02274 , H01L21/02345 , H01L21/28273 , H01L21/3105 , H01L21/31612 , H01L29/42332 , H01L29/7883
摘要： In a method of forming a thin layer having a desired composition, a source gas is provided onto a substrate loaded in a chamber for a first time, and the source gas is chemisorbed onto the substrate. While the source gas is provided, a plasma is generated in the chamber for a second time to change the chemisorbed source gas into the thin layer having the desired composition. The thin layer may have a stoichiometrical composition or a non-stoichiometrical composition.

83. 发明申请

US20060197131A1 DRAM device and method of manufacturing the same 失效
标题翻译： DRAM装置及其制造方法
公开(公告)号：US20060197131A1
公开(公告)日：2006-09-07
申请号：US11358060
申请日：2006-02-22
申请人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
发明人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
IPC分类号： H01L29/94
CPC分类号： H01L27/10873 , H01L27/10829
摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.
摘要翻译：在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。非导电图案具有比导电图案的带隙大的带隙。在MTJ结构的侧壁上形成栅极绝缘层和栅电极。字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因此DRAM器件需要较小的衬底表面积。

84. 发明授权

US06514827B2 Method for fabricating a dual metal gate for a semiconductor device 失效
标题翻译：半导体器件的双金属栅极的制造方法
公开(公告)号：US06514827B2
公开(公告)日：2003-02-04
申请号：US10034529
申请日：2001-12-28
申请人： Tae Kyun Kim , Se Aug Jang , Tae Ho Cha , In Seok Yeo
发明人： Tae Kyun Kim , Se Aug Jang , Tae Ho Cha , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/823842
摘要： A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first region. The first region is either the PMOS or NMOS region, and the remaining region becomes a second region. A dummy gate is formed in the second region. A spacer and a source/drain region are formed for each of the first and dummy gates. The dummy gate, however, is removed to expose a portion of the substrate in the second region. A second gate constructed of a second gate insulating layer and a second metal layer is then formed on the exposed portion of the substrate in the second region.
摘要翻译：一种用于制造半导体器件的双金属栅极结构的方法，包括具有PMOS和NMOS区域的半导体衬底的沉积，在第一区域中形成具有第一绝缘层和第一金属层的第一栅极。第一区域是PMOS或NMOS区域，其余区域成为第二区域。在第二区域中形成伪栅极。为第一和虚拟栅极中的每一个形成间隔物和源极/漏极区域。然而，去除伪栅极以暴露第二区域中的衬底的一部分。然后在第二区域中的衬底的暴露部分上形成由第二栅极绝缘层和第二金属层构成的第二栅极。

85. 发明授权

US06468914B1 Method of forming gate electrode in semiconductor device 失效
标题翻译：在半导体器件中形成栅电极的方法
公开(公告)号：US06468914B1
公开(公告)日：2002-10-22
申请号：US09472541
申请日：1999-12-27
申请人： Se Aug Jang , In Seok Yeo
发明人： Se Aug Jang , In Seok Yeo
IPC分类号： H01L2144
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/6659
摘要： A method of forming a gate electrode in a semiconductor device which can prevent abnormal oxidation of a titanium silicide layer when performing gate re-oxidation process after a gate electrode having a stacked structure of a doped polysilicon layer and the titanium silicide layer.
摘要翻译：一种在半导体器件中形成栅电极的方法，其可以在具有掺杂多晶硅层和硅化钛层的堆叠结构的栅极之后执行栅极再氧化处理时防止硅化钛层的异常氧化。

86. 发明授权

US06340629B1 Method for forming gate electrodes of semiconductor device using a separated WN layer 失效
标题翻译：使用分离的WN层形成半导体器件的栅电极的方法
公开(公告)号：US06340629B1
公开(公告)日：2002-01-22
申请号：US09466752
申请日：1999-12-17
申请人： In Seok Yeo , Jean Hong Lee
发明人： In Seok Yeo , Jean Hong Lee
IPC分类号： H01L213205
CPC分类号： H01L21/28061 , H01L29/4941
摘要： Disclosed is a method for forming gate electrodes using tungsten formed on a tungsten nitride layer by the chemical vapor deposition(CVD) process rather than the physical vapor deposition(PVD) process. According to the method for forming gate electrodes of the present invention, a silicon layer is formed as a conductive layer for gate electrodes. A tungsten nitride layer is formed on the silicon layer, and then the tungsten nitride layer is thermally treated thereby making a surface of the tungsten nitride layer a first tungsten layer. Next, a second tungsten layer is formed by using the first tungsten layer as a nucleation layer according to the CVD process. According to the present method for forming gate electrodes, tungsten can be deposited by the CVD process rather than by the PVD process. Therefore, those problems such as washing equipment and the particle source which are necessarily accompanied with the PVD process can be prevented, thereby improving productivity and yield.
摘要翻译：公开了一种通过化学气相沉积（CVD）工艺而不是物理气相沉积（PVD）工艺在钨氮化物层上形成钨的栅电极的形成方法。根据本发明的栅极形成方法，形成硅层作为栅电极的导电层。在硅层上形成氮化钨层，然后对氮化钨层进行热处理，从而使氮化钨层的表面成为第一钨层。接下来，通过根据CVD工艺使用第一钨层作为成核层形成第二钨层。根据用于形成栅电极的本方法，可以通过CVD工艺而不是通过PVD工艺沉积钨。因此，可以防止必须伴随PVD工艺的洗涤设备和粒子源等问题，从而提高生产率和产率。

87. 发明授权

US06255206B1 Method of forming gate electrode with titanium polycide structure 有权
标题翻译：用聚硅氧烷结构形成栅电极的方法
公开(公告)号：US06255206B1
公开(公告)日：2001-07-03
申请号：US09434647
申请日：1999-11-05
申请人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
发明人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
IPC分类号： H01L213205
CPC分类号： H01L21/28061 , H01L21/31683
摘要： A method of forming a gate electrode with a titanium polycide structure which can prevent abnormal oxidation of the gate electrode and reduce the resistivity of the gate electrode when performing a re-oxidation process, is disclosed. According to the present invention, a gate oxide layer, a polysilicon layer and a titanium silicide layer are formed on a semiconductor substrate, in sequence. A mask insulating layer is then formed in the shape of a gate electrode on the titanium silicide layer and the titanium silicide layer and the polysilicon layer are etched using the mask insulating layer to form a gate electrode. Thereafter, the substrate is oxidized using re-oxidation process to form an oxide layer with a uniform thickness on the side wall of the gate electrode and on the surface of the substrate. Here, the re-oxidation process is performed at the temperature of 750° C. or less using dry oxidation. Furthermore, the re-oxidation process is performed at the temperature of 700 to 750° C. and the oxide layer is formed to the thickness of 30 to 60 Å, preferably, about 50 Å.
摘要翻译：公开了一种形成具有可以防止栅电极的异常氧化并降低栅电极的电阻率的多晶硅化钛结构的栅电极的方法。根据本发明，栅极氧化物层在半导体衬底上依次形成多晶硅层和硅化钛层。然后在硅化钛层上形成栅极形状的掩模绝缘层，并且使用掩模绝缘层蚀刻钛硅化物层和多晶硅层以形成栅电极。此后，使用再氧化工艺氧化基板，在栅电极的侧壁和基板的表面上形成均匀厚度的氧化物层。这里，使用干式氧化在750℃以下的温度下进行再氧化处理。此外，再次氧化处理在700-750℃的温度下进行，氧化物层的厚度形成为30至60埃，优选为约50埃。

88. 发明授权

US6107144A Method for forming field oxide of semiconductor device and the semiconductor device 失效
标题翻译：用于形成半导体器件的场氧化物的方法和半导体器件
公开(公告)号：US6107144A
公开(公告)日：2000-08-22
申请号：US70911
申请日：1998-05-04
申请人： Se Aug Jang , Young Bog Kim , In Seok Yeo , Jong Choul Kim
发明人： Se Aug Jang , Young Bog Kim , In Seok Yeo , Jong Choul Kim
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76202
摘要： A method for forming a field oxide of a semiconductor device and the semiconductor device. In order to form the field oxide, first, an element isolation mask is constructed on a semiconductor substrate. Then, a nitride spacer is formed at the side wall of the mask. At this time, a nitrogen-containing polymer is produced on the field region. The exposed region of the semiconductor substrate is oxidized at a temperature of 1,050-1,200.degree. C. to grow a recess-oxide while transforming the nitrogen-containing polymer into a nitride. Thereafter, the recess oxide is removed, together with the nitride, to create a trench in which the field oxide is formed through thermal oxidation. Therefore, the method can prevent an FOU phenomenon upon the growth of a field oxide and improve the field oxide thinning effect, thereby bringing a significant improvement to the production yield and the reliability of a semiconductor device.
摘要翻译：一种用于形成半导体器件的场氧化物和半导体器件的方法。为了形成场氧化物，首先，在半导体衬底上构造元件隔离掩模。然后，在掩模的侧壁上形成氮化物间隔物。此时，在场区域产生含氮聚合物。半导体衬底的暴露区域在1050〜1200℃的温度下被氧化，生长凹陷氧化物，同时将含氮聚合物转化为氮化物。此后，与氮化物一起去除凹陷氧化物，以产生通过热氧化形成场氧化物的沟槽。因此，该方法可以防止场氧化物生长时的FOU现象，提高场氧化物稀化效果，从而显着提高半导体器件的制造成品率和可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式