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71. 发明授权

US07495900B2 Protection mechanism for connectors 失效
标题翻译：连接器保护机构
公开(公告)号：US07495900B2
公开(公告)日：2009-02-24
申请号：US11306452
申请日：2005-12-29
申请人： Shu-Gang Shi , Yu Huang
发明人： Shu-Gang Shi , Yu Huang
IPC分类号： G06F1/16
CPC分类号： G06F1/181
摘要： A protection mechanism in accordance with a preferred embodiment of the present invention includes a bracket for being secured to a rear portion of a computer chassis, and first and second covers respectively pivotally attached to the bracket. Adjacent sides of the first and second covers each form a lug. The lug of the first cover abuts against the lug of the second cover so as to prevent the second cover from rotating.
摘要翻译：根据本发明的优选实施例的保护机构包括用于固定到计算机机箱的后部的支架，以及分别枢转地附接到支架的第一和第二盖。第一和第二盖的相邻侧各自形成凸耳。第一盖的凸耳抵靠第二盖的凸耳，以防止第二盖旋转。

72. 发明授权

US07333689B2 Photonic integrated devices having reduced absorption loss 有权
标题翻译：具有降低吸收损耗的光子集成器件
公开(公告)号：US07333689B2
公开(公告)日：2008-02-19
申请号：US11241003
申请日：2005-09-30
申请人： Vinod M. Menon , Milind R. Gokhale , Stephen R. Forrest , Yu Huang , Fengnian Xia
发明人： Vinod M. Menon , Milind R. Gokhale , Stephen R. Forrest , Yu Huang , Fengnian Xia
IPC分类号： G02B6/26 , G02B6/10
CPC分类号： H01S5/1082 , B82Y20/00 , G02B6/1228 , H01S5/065 , H01S5/1014 , H01S5/1032 , H01S5/162 , H01S5/3213 , H01S5/34306
摘要： An asymmetric twin waveguide (ATG) structure with quantum-well intermixing in the taper region of the active waveguide is disclosed. The structure comprises a first waveguide, a second waveguide, and a taper formed in the second waveguide. The taper has an intermixed area formed therein comprising a plurality of quantum wells intermixed with a plurality of barriers. The quantum wells and barriers may be intermixed using plasma-enhanced intermixing such as, for example, Argon plasma enhanced intermixing. Quantum-well intermixing reduces absorption loss normally encountered in the movement of light between waveguides.
摘要翻译：公开了在有源波导的锥形区域中具有量子阱混合的不对称双波导（ATG）结构。该结构包括第一波导，第二波导和形成在第二波导中的锥形。该锥形件具有形成在其中的混合区域，其包括与多个屏障混合的多个量子阱。量子阱和屏障可以使用等离子体增强混合（例如，氩等离子体增强混合）混合。量子阱混合减少了在波导之间光的移动中通常遇到的吸收损耗。

73. 发明申请

US20070032051A1 Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices 有权
公开(公告)号：US20070032051A1
公开(公告)日：2007-02-08
申请号：US11543336
申请日：2006-10-04
申请人： Charles Lieber , Yi Cui , Xiangfeng Duan , Yu Huang
发明人： Charles Lieber , Yi Cui , Xiangfeng Duan , Yu Huang
IPC分类号： H01G9/20
CPC分类号： H01L29/0665 , B01J23/50 , B01J23/52 , B01J23/72 , B01J35/0013 , B01J37/349 , B81C1/0019 , B81C1/00206 , B82Y10/00 , B82Y15/00 , B82Y30/00 , B82Y40/00 , C30B11/00 , C30B25/005 , C30B29/605 , G01N27/4146 , G01N33/54373 , G11C13/0014 , G11C13/0019 , G11C13/025 , G11C13/04 , G11C2213/77 , G11C2213/81 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/02543 , H01L21/02557 , H01L21/0256 , H01L21/02573 , H01L21/02581 , H01L21/02603 , H01L21/02606 , H01L21/0262 , H01L21/02628 , H01L21/02631 , H01L21/02636 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L23/53276 , H01L29/045 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/1602 , H01L29/18 , H01L29/20 , H01L29/207 , H01L29/22 , H01L29/24 , H01L29/26 , H01L29/267 , H01L33/06 , H01L33/18 , H01L33/20 , H01L51/002 , H01L51/0048 , H01L2924/0002 , Y02E10/549 , Y02P70/521 , Y10S438/962 , Y10S977/762 , Y10S977/847 , Y10S977/858 , Y10S977/882 , Y10S977/883 , Y10S977/892 , Y10S977/936 , Y10T428/24 , H01L2924/00
摘要： A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

74. 发明申请

US20060282577A1 Universal serial bus data transport method and device 有权
标题翻译：通用串行总线数据传输方法及装置
公开(公告)号：US20060282577A1
公开(公告)日：2006-12-14
申请号：US11339173
申请日：2006-01-24
申请人： Yu Huang , Zhou Lu , Fan Chen
发明人： Yu Huang , Zhou Lu , Fan Chen
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A Universal Serial Bus data transport method and its device is disclosed. Data transport is performed through a high-speed transport technique based on a Universal Serial Bus, which consists of Universal Serial Bus protocol for communication between the device and the host, and SCSI protocol for interaction between the device and the upper driver layer. A data transport device using the Universal Serial Bus thus uses the embedded driver inside the operating system, which may be self-loaded/self-initialized, and have high data transport speed, and convenient to use.
摘要翻译：公开了一种通用串行总线数据传输方法及其装置。通过基于通用串行总线的高速传输技术来执行数据传输，该通用串行总线由用于设备和主机之间的通信的通用串行总线协议和用于设备与上层驱动器层之间的交互的SCSI协议组成。因此，使用通用串行总线的数据传输装置使用操作系统内的嵌入式驱动器，其可以是自载/自初始化，并具有高数据传输速度，并且使用方便。

75. 发明申请

US20060279933A1 Heat dissipating device with back plate for electronic assembly 失效
标题翻译：散热装置，带背板用于电子组装
公开(公告)号：US20060279933A1
公开(公告)日：2006-12-14
申请号：US11269379
申请日：2005-11-08
申请人： Hsieh-Kun Lee , Chun-Chi Chen , Shin-Hsuu Wung , Yu Huang
发明人： Hsieh-Kun Lee , Chun-Chi Chen , Shin-Hsuu Wung , Yu Huang
IPC分类号： H05K7/20
CPC分类号： H01L23/4093 , H01L2924/0002 , H01L2924/00
摘要： An electronic assembly includes a PCB (20), a socket (22) mounted on the PCB, a CPU (24) connected with the socket, a heat sink (10) in thermal contact with the CPU, a foldable back plate (30) attached to an underside of the PCB and a base plane (40) forming four bridges (42). The back plate includes a first piece section (32) and a second piece section (34) pivotally joined together by a pivot (36). The first and the second piece sections each comprise two legs inserted into two corresponding bridges. Screws are used to extend through the heat sink, the PCB, the bridges to threadedly engage with the legs of the back plate, respectively. The pivot is located under a part of the PCB at which the CPU is mounted.
摘要翻译：电子组件包括PCB（20），安装在PCB上的插座（22），与插座连接的CPU（24），与CPU热接触的散热器（10），可折叠背板（30）附接到PCB的下侧和形成四个桥（42）的基面（40）。后板包括通过枢轴（36）枢轴连接在一起的第一片段（32）和第二片段（34）。第一和第二片段各自包括插入到两个对应的桥中的两个腿。螺丝用于延伸穿过散热片，PCB，桥接件分别与背板的腿部螺纹接合。枢轴位于安装有CPU的PCB的一部分下方。

76. 发明申请

US20060175601A1 Nanoscale wires and related devices 审中-公开
公开(公告)号：US20060175601A1
公开(公告)日：2006-08-10
申请号：US11172408
申请日：2005-06-30
申请人： Charles Lieber , Xiangfeng Duan , Yi Cui , Yu Huang , Mark Gudiksen , Lincoln Lauhon , Jianfang Wang , Hongkun Park , Qingqiao Wei , Wenjie Liang , David Smith , Deli Wang , Zhaohui Zhong
发明人： Charles Lieber , Xiangfeng Duan , Yi Cui , Yu Huang , Mark Gudiksen , Lincoln Lauhon , Jianfang Wang , Hongkun Park , Qingqiao Wei , Wenjie Liang , David Smith , Deli Wang , Zhaohui Zhong
IPC分类号： H01L31/109
CPC分类号： C30B29/60 , B82Y10/00 , B82Y15/00 , B82Y30/00 , G01N27/4146 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/1606 , H01L29/2003 , H01L29/267 , H01L29/73 , H01L31/0352 , H01L31/08 , H01L33/18 , H01L33/20 , H01L51/0048
摘要： The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

77. 发明申请

US20060141211A1 Highly heat-transferring substrate and process of manufacturing the same 审中-公开
标题翻译：高度传热的基材及其制造方法
公开(公告)号：US20060141211A1
公开(公告)日：2006-06-29
申请号：US11019259
申请日：2004-12-23
申请人： Yu Huang , Min-Chung Lu
发明人： Yu Huang , Min-Chung Lu
IPC分类号： B32B3/10
CPC分类号： H05K3/445 , B32B3/266 , B32B15/06 , B32B15/18 , B32B15/20 , B32B2250/40 , B32B2307/202 , B32B2307/206 , B32B2307/302 , B32B2307/538 , B32B2457/08 , H05K1/056 , H05K3/382 , H05K2201/0355 , Y10T428/12986 , Y10T428/24322
摘要： A highly heat-transferring substrate is manufactured by drilling holes on a metal material of high heat conductivity, such as aluminum; positioning the metal material between two copper foil layers; applying a highly heat-transferring gum between the metal material and the copper foil layers; and melting the gum using a high temperature produced during pressing the metal material and the copper foil layers together. The melted gum bonds the metal material to the copper foil layers and flows into the holes on the metal material to form an insulating coating, which allows the finished substrate to be drilled and plated without the risk of short circuit caused by contacted metal material and plated coating.
摘要翻译：通过在诸如铝的高导热性金属材料上钻孔，制造高度传热的基板; 将金属材料定位在两个铜箔层之间; 在金属材料和铜箔层之间施加高度传热的胶; 并且使用在将金属材料和铜箔层压在一起时产生的高温来熔融口香糖。熔融的胶将金属材料粘合到铜箔层上并流入金属材料上的孔中以形成绝缘涂层，这使得成品基材可以被钻孔和镀覆，而不会由接触的金属材料引起短路并且被电镀涂层。

78. 发明申请

US20060111873A1 Compactor independent direct diagnosis of test hardware 有权
标题翻译：压缩机独立直接诊断测试硬件
公开(公告)号：US20060111873A1
公开(公告)日：2006-05-25
申请号：US11267221
申请日：2005-11-04
申请人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G21C17/00
CPC分类号： G01R31/318547 , G06F11/267 , G06F11/27
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在一个示例性实施例中，接收到故障日志，其包括指示对链模式的压缩测试响应的条目和对扫描模式的压缩测试响应。至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。可以报告一个或多个识别的扫描单元候选。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

79. 发明申请

US20050164432A1 Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices 有权
公开(公告)号：US20050164432A1
公开(公告)日：2005-07-28
申请号：US11082372
申请日：2005-03-17
申请人： Charles Lieber , Yi Cui , Xiangfeng Duan , Yu Huang
发明人： Charles Lieber , Yi Cui , Xiangfeng Duan , Yu Huang
IPC分类号： H01L29/73 , C30B11/00 , C30B25/00 , G01N27/12 , G01N27/414 , G01N33/543 , G11C13/02 , H01L21/329 , H01L21/331 , H01L23/532 , H01L27/10 , H01L29/06 , H01L29/207 , H01L29/267 , H01L29/88 , H01L33/06 , H01L33/18 , H01L51/00 , H01L51/30 , H01L21/00 , H01L21/84
CPC分类号： H01L29/0665 , B01J23/50 , B01J23/52 , B01J23/72 , B01J35/0013 , B01J37/349 , B81C1/0019 , B81C1/00206 , B82Y10/00 , B82Y15/00 , B82Y30/00 , B82Y40/00 , C30B11/00 , C30B25/005 , C30B29/605 , G01N27/4146 , G01N33/54373 , G11C13/0014 , G11C13/0019 , G11C13/025 , G11C13/04 , G11C2213/77 , G11C2213/81 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/02543 , H01L21/02557 , H01L21/0256 , H01L21/02573 , H01L21/02581 , H01L21/02603 , H01L21/02606 , H01L21/0262 , H01L21/02628 , H01L21/02631 , H01L21/02636 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L23/53276 , H01L29/045 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/1602 , H01L29/18 , H01L29/20 , H01L29/207 , H01L29/22 , H01L29/24 , H01L29/26 , H01L29/267 , H01L33/06 , H01L33/18 , H01L33/20 , H01L51/002 , H01L51/0048 , H01L2924/0002 , Y02E10/549 , Y02P70/521 , Y10S438/962 , Y10S977/762 , Y10S977/847 , Y10S977/858 , Y10S977/882 , Y10S977/883 , Y10S977/892 , Y10S977/936 , Y10T428/24 , H01L2924/00
摘要： A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and my have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

80. 发明授权

US06919736B1 Field programmable gate array having embedded memory with configurable depth and width 有权
标题翻译：具有可配置深度和宽度的嵌入式存储器的现场可编程门阵列
公开(公告)号：US06919736B1
公开(公告)日：2005-07-19
申请号：US10620286
申请日：2003-07-14
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Bai Nguyen , Yu Huang , Jack Wong
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Bai Nguyen , Yu Huang , Jack Wong
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/17796 , G06F17/5054
摘要： A field programmable gate array (FPGA) has plural columns of run-time memory provided in each of one or more partitions. Each column of run-time memory has a plurality of configurable memory blocks (CMB's). Each CMB is programmably configurable at least into a shallow-and-widest mode where data words have a maximum bit width and into a deep-and-narrowest mode where data words have a minimum bit width. Each CMB spans plural interconnect buses and the bits of its widest data words are distributed among the spanned interconnect buses. When a deep-and-narrow mode is invoked, CMB's of alternate columns operate in complementary fashion so that bits of narrowed words from one CMB move through a first subset of the interconnect buses while bits of narrowed words from a second CMB, in an alternate column, move through a second subset of the interconnect buses, where the second subset is mutually exclusive of the first subset of the interconnect buses. On the other hand, when the shallow-and-widest mode is invoked, the bits of the wide words of CMB's in alternate columns shared interconnect buses on an overlapping basis. In one embodiment, the shared interconnect buses are tri-statable. Programmable joiners are provided for joining or disjoining the tri-statable interconnect buses of adjacent partitions.
摘要翻译：现场可编程门阵列（FPGA）具有在一个或多个分区中的每一个中提供的多列运行时存储器。每列运行时存储器具有多个可配置存储器块（CMB）。每个CMB可编程地至少配置为浅和最宽的模式，其中数据字具有最大位宽度，并且成为数据字具有最小位宽度的最深和最窄模式。每个CMB跨越多个互连总线，其最宽的数据字的位分布在跨接互连总线之间。当调用深而窄的模式时，CMB的备用列以互补方式运行，使得来自一个CMB的窄字的位移动通过互连总线的第一子集，同时来自第二CMB的窄字的位置列移动穿过互连总线的第二子集，其中第二子集与互连总线的第一子集相互排斥。另一方面，当调用浅和最宽模式时，CMB在备用列中的宽字的位以重叠的基础共享互连总线。在一个实施例中，共享互连总线是三态的。可编程连接器用于连接或分离相邻分区的三态互连总线。

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