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71. 发明授权

US06943373B2 Semiconductor memory device using vertical-channel transistors 失效
公开(公告)号：US06943373B2
公开(公告)日：2005-09-13
申请号：US10693987
申请日：2003-10-28
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： G11C11/41 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/10 , H01L29/72
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

72. 发明授权

US06828242B2 Method for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06828242B2
公开(公告)日：2004-12-07
申请号：US10223317
申请日：2002-08-20
申请人： Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
发明人： Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
IPC分类号： H01L21302
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28247 , H01L21/76897 , H01L27/10811 , H01L27/10814 , H01L27/10873 , H01L29/4941
摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
摘要翻译：公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。然后，在这些膜的侧壁上形成侧壁膜。此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加被阻止

73. 发明授权

US06825504B2 Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06825504B2
公开(公告)日：2004-11-30
申请号：US10277152
申请日：2002-10-22
申请人： Hiroyasu Ishizuka , Kousuke Okuyama , Katsuhiko Kubota
发明人： Hiroyasu Ishizuka , Kousuke Okuyama , Katsuhiko Kubota
IPC分类号： H01L2972
CPC分类号： H01L27/0262
摘要： In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.
摘要翻译：为了消除由施加到外部端子的过大电压的极性引起的ESD电阻的差异，并且提高半导体集成电路器件对正负过电压的ESD电阻，具有可控硅结构的保护元件，用于保护内部在外部端子和地电位之间设置有来自正过电压的电路和由用于保护内部电路免于负过电压的二极管D1构成的保护元件。

74. 发明授权

US06545311B2 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US06545311B2
公开(公告)日：2003-04-08
申请号：US09942825
申请日：2001-08-31
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (G03) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.
摘要翻译：基于包括一对差分形式的非易失性存储器元件的存储单元的信息保持能力得到改善。构成闪速存储器的非易失性存储元件（130）的结构使得其隧道氧化膜（G03）和浮栅电极（FGT）分别通过利用晶体管的栅极氧化膜（GT2）和栅电极（GT2）形成用于形成在与元件（130）的半导体衬底相同的半导体衬底上的电路。存储单元以2单元/ 1位方案构成，其中一对非易失性存储器元件可以分别连接到一对互补数据线，并且为非易失性存储元件设置彼此不同的阈值电压状态以便差异地读出数据。读出模式中的字线电压被设定为与热平衡状态（初始阈值电压）中的阈值电压基本相等，并且基本上等于低阈值电压值和高阈值的平均值电压值。因此，增强数据保持能力以实现读出故障率的降低。

75. 发明授权

US06528839B2 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US06528839B2
公开(公告)日：2003-03-04
申请号：US09942902
申请日：2001-08-31
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.
摘要翻译：基于包括一对差分形式的非易失性存储器元件的存储单元的信息保持能力得到改善。构成闪速存储器的非易失性存储元件（130）被构造成通过利用晶体管的栅极氧化膜（GT2）和栅电极（GT2）分别形成隧道氧化膜（GO3）和浮栅电极（FGT）用于形成在与元件（130）的半导体衬底相同的半导体衬底上的电路。存储单元以2单元/ 1位方案构成，其中一对非易失性存储器元件可以分别连接到一对互补数据线，并且为非易失性存储元件设置彼此不同的阈值电压状态以便差异地读出数据。读出模式中的字线电压被设定为与热平衡状态（初始阈值电压）中的阈值电压基本相等，并且基本上等于低阈值电压值和高阈值的平均值电压值。因此，增强数据保持能力以实现读出故障率的降低。

76. 发明授权

US5436484A Semiconductor integrated circuit device having input protective elements and internal circuits 失效
标题翻译：具有输入保护元件和内部电路的半导体集成电路器件
公开(公告)号：US5436484A
公开(公告)日：1995-07-25
申请号：US143151
申请日：1993-10-29
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

77. 发明授权

US5276346A Semiconductor integrated circuit device having protective/output elements and internal circuits 失效
标题翻译：具有保护/输出元件和内部电路的半导体集成电路器件
公开(公告)号：US5276346A
公开(公告)日：1994-01-04
申请号：US815863
申请日：1992-01-02
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：本发明公开了一种半导体器件，其具有由静电场保护电路保护的内部电路，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一个实施例，提供一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

78. 发明授权

US4784968A Process for manufacturing a semiconductor device having MIS-type field effect transistors with impurity region below the gate electrode 失效
标题翻译：具有MIS栅型电极下方杂质区域的MIS型场效应晶体管的半导体器件的制造方法
公开(公告)号：US4784968A
公开(公告)日：1988-11-15
申请号：US75411
申请日：1987-07-20
申请人： Kazuhiro Komori , Kenichi Kuroda , Kousuke Okuyama
发明人： Kazuhiro Komori , Kenichi Kuroda , Kousuke Okuyama
IPC分类号： H01L29/10 , H01L29/78 , H01L21/265 , B01J17/00
CPC分类号： H01L29/1083 , H01L29/1033 , H01L29/78 , Y10S438/919
摘要： Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.
摘要翻译：这里公开了一种MOS型场效应晶体管，其中在沟道下方形成具有与衬底相同类型的导电性并且杂质浓度高于衬底的半导体区域，以使其两端处于接触状态与源极和漏极区域。半导体区域限制耗尽层从源极和漏极区域的延伸，并限制短沟道效应。在半导体区域和源极和漏极区域之间的结电容小。

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