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71. 发明授权

US07217950B2 Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same 有权
标题翻译：具有异质结的绝缘栅隧道注入装置及其制造方法
公开(公告)号：US07217950B2
公开(公告)日：2007-05-15
申请号：US10682154
申请日：2003-10-10
申请人： Saichirou Kaneko , Masakatsu Hoshi , Kraisorn Throngnumchai , Tetsuya Hayashi , Hideaki Tanaka , Teruyoshi Mihara
发明人： Saichirou Kaneko , Masakatsu Hoshi , Kraisorn Throngnumchai , Tetsuya Hayashi , Hideaki Tanaka , Teruyoshi Mihara
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/0878 , H01L29/1602 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7813 , H01L29/7828
摘要： The present invention-provides a tunnel-injection device which encompasses, a reception layer made of a first semiconductor, a barrier-forming layer made of a second semiconductor having a bandgap-narrower than the first semiconductor, being in metallurgical contact with the reception layer, a gate insulating film disposed on the barrier-forming layer. The gate electrode controls the width of the barrier generated at the heterojunction interface between the reception layer and the barrier-forming layer so as to change the tunneling probability of carriers through the barrier. The device further encompasses a carrier receiving region being contact with the reception layer and a carrier-supplying region being contact with the barrier-forming layer.
摘要翻译：本发明提供了一种隧道注入装置，其包括由第一半导体制成的接收层，由具有窄于第一半导体带隙的第二半导体制成的阻挡层形成层与接收层冶金接触设置在阻挡层形成层上的栅极绝缘膜。栅电极控制在接收层和阻挡层形成层之间的异质结界面处产生的势垒的宽度，以便改变载流子穿过屏障的隧穿概率。该装置还包括与接收层接触的载体接收区域和与阻挡层形成层接触的载体供给区域。

72. 发明申请

US20050012143A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050012143A1
公开(公告)日：2005-01-20
申请号：US10872772
申请日：2004-06-22
申请人： Hideaki Tanaka , Masakatsu Hoshi , Tetsuya Hayashi , Saichirou Kaneko
发明人： Hideaki Tanaka , Masakatsu Hoshi , Tetsuya Hayashi , Saichirou Kaneko
IPC分类号： H01L21/04 , H01L29/24 , H01L29/267 , H01L29/49 , H01L29/739 , H01L29/78 , H01L21/331
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/165 , H01L29/4966 , H01L29/66068 , H01L29/739 , H01L29/78 , H01L29/7802 , H01L29/7804 , H01L29/7813 , H01L29/7838
摘要： An aspect of the present invention provides a semiconductor device that includes a semiconductor base including, a semiconductor substrate of a first conductivity type and a drain region of the first conductivity type formed on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, a gate electrode insulated from the semiconductor base by a gate insulating film, the gate electrode made of a semiconductor material, a built-in potential difference between a region and the gate electrode made of the semiconductor material is greater than that of polysilicon having as high impurity concentration as possible, the region is a part of the drain region adjacent to the gate electrode through the gate insulating film.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括半导体基底，该半导体基底包括在半导体衬底上形成的第一导电类型的半导体衬底和第一导电类型的漏极区，并且具有比半导体衬底更低的杂质浓度，通过栅极绝缘膜与半导体基底绝缘的栅电极，由半导体材料制成的栅电极，由半导体材料制成的区域和栅电极之间的内置电位差大于具有高半导体材料的多晶硅的内部电位差杂质浓度尽可能地，该区域是通过栅极绝缘膜与栅电极相邻的漏极区域的一部分。

73. 发明授权

US08786011B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08786011B2
公开(公告)日：2014-07-22
申请号：US13643468
申请日：2011-04-27
申请人： Shigeharu Yamagami , Tetsuya Hayashi , Tatsuhiro Suzuki
发明人： Shigeharu Yamagami , Tetsuya Hayashi , Tatsuhiro Suzuki
IPC分类号： H01L29/66 , H01L29/165 , H01L29/10 , H01L21/8234 , H01L29/06 , H01L29/78 , H01L21/82 , H01L27/07 , H01L29/861 , H01L29/872 , H01L29/16 , H01L21/04 , H01L29/20
CPC分类号： H01L21/8213 , H01L21/046 , H01L21/0485 , H01L21/823487 , H01L27/0727 , H01L29/0619 , H01L29/0696 , H01L29/0865 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/165 , H01L29/2003 , H01L29/6606 , H01L29/66068 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： Each insulating gate portion forms a channel in part of a first well region located between a drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface of the drift region to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface.
摘要翻译：每个绝缘栅极部分在位于漂移区域和源极区域之间的第一阱区域的一部分中形成沟道。第一主电极与漂移区的主表面露出的部分漂移区形成结，以构成单极二极管并连接到第一阱区和源极区。当从主表面的法线方向观察时，多个绝缘栅极部分具有彼此平行的线状图案。在每对相邻的绝缘栅极部分之间，沿着绝缘栅极部分延伸的方向布置有第一主电极与漂移区域连接的接合部分和第一阱区域。通道至少沿主表面的法线方向形成。

74. 发明申请

US20130043524A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130043524A1
公开(公告)日：2013-02-21
申请号：US13643468
申请日：2011-03-27
申请人： Shigeharu Yamagami , Tetsuya Hayashi , Tatsuhiro Suzuki
发明人： Shigeharu Yamagami , Tetsuya Hayashi , Tatsuhiro Suzuki
IPC分类号： H01L29/78
CPC分类号： H01L21/8213 , H01L21/046 , H01L21/0485 , H01L21/823487 , H01L27/0727 , H01L29/0619 , H01L29/0696 , H01L29/0865 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/165 , H01L29/2003 , H01L29/6606 , H01L29/66068 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： Each insulating gate portion forms a channel in part of a first well region located between a drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface of the drift region to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface.
摘要翻译：每个绝缘栅极部分在位于漂移区域和源极区域之间的第一阱区域的一部分中形成沟道。第一主电极与漂移区的主表面露出的部分漂移区形成结，以构成单极二极管并连接到第一阱区和源极区。当从主表面的法线方向观察时，多个绝缘栅极部分具有彼此平行的线状图案。在每对相邻的绝缘栅极部分之间，沿着绝缘栅极部分延伸的方向布置有第一主电极与漂移区域连接的接合部分和第一阱区域。通道至少沿主表面的法线方向形成。

75. 发明申请

US20140042523A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140042523A1
公开(公告)日：2014-02-13
申请号：US14112097
申请日：2012-02-24
申请人： Shigeharu Yamagami , Tetsuya Hayashi , Taku Shimomura
发明人： Shigeharu Yamagami , Tetsuya Hayashi , Taku Shimomura
IPC分类号： H01L29/78
CPC分类号： H01L29/7801 , H01L27/0629 , H01L29/0623 , H01L29/1608 , H01L29/165 , H01L29/41766 , H01L29/4238 , H01L29/66068 , H01L29/7803 , H01L29/7805 , H01L29/7806 , H01L29/7813
摘要： An anode region 106 is formed on a bottom portion of a trench 105 in which a gate electrode 108 is formed or in a drift region 102 immediately under the trench 105. A contact hole 110 is formed in the trench 105 at a depth reaching the anode region 106. A source electrode 112 is embedded in the contact hole 110 while interposing an inner wall insulating film 111 therebetween. The anode region 106 and the source electrode 112 are electrically connected to each other in a state of being insulated from the gate electrode 108 by the inner wall insulating film 111.
摘要翻译：阳极区域106形成在其中形成有栅电极108的沟槽105的底部或沟槽105正下方的漂移区域102中。接触孔110在到达阳极的深度处形成在沟槽105中源电极112嵌入在接触孔110中，同时在其间插入内壁绝缘膜111。阳极区域106和源极电极112通过内壁绝缘膜111与栅电极108绝缘的状态彼此电连接。

76. 发明授权

US09252261B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US09252261B2
公开(公告)日：2016-02-02
申请号：US14112097
申请日：2012-02-24
申请人： Shigeharu Yamagami , Tetsuya Hayashi , Taku Shimomura
发明人： Shigeharu Yamagami , Tetsuya Hayashi , Taku Shimomura
IPC分类号： H01L29/78 , H01L29/417 , H01L27/06 , H01L29/66 , H01L29/165 , H01L29/06 , H01L29/423 , H01L29/16
CPC分类号： H01L29/7801 , H01L27/0629 , H01L29/0623 , H01L29/1608 , H01L29/165 , H01L29/41766 , H01L29/4238 , H01L29/66068 , H01L29/7803 , H01L29/7805 , H01L29/7806 , H01L29/7813
摘要： An anode region 106 is formed on a bottom portion of a trench 105 in which a gate electrode 108 is formed or in a drift region 102 immediately under the trench 105. A contact hole 110 is formed in the trench 105 at a depth reaching the anode region 106. A source electrode 112 is embedded in the contact hole 110 while interposing an inner wall insulating film 111 therebetween. The anode region 106 and the source electrode 112 are electrically connected to each other in a state of being insulated from the gate electrode 108 by the inner wall insulating film 111.
摘要翻译：阳极区域106形成在其中形成有栅电极108的沟槽105的底部或沟槽105正下方的漂移区域102中。接触孔110在到达阳极的深度处形成在沟槽105中源电极112嵌入在接触孔110中，同时在其间插入内壁绝缘膜111。阳极区域106和源极电极112通过内壁绝缘膜111与栅电极108绝缘的状态彼此电连接。

77. 发明授权

US07042086B2 Stacked semiconductor module and assembling method of the same 有权
标题翻译：堆叠半导体模块及其组装方法相同
公开(公告)号：US07042086B2
公开(公告)日：2006-05-09
申请号：US10678208
申请日：2003-10-06
申请人： Yoshio Shimoida , Toshiro Shinohara , Tetsuya Hayashi , Masanori Yamagiwa
发明人： Yoshio Shimoida , Toshiro Shinohara , Tetsuya Hayashi , Masanori Yamagiwa
IPC分类号： H01L23/34
CPC分类号： H01L25/071 , H01L2224/04026 , H01L2224/06181 , H01L2224/32245 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A stacked semiconductor module encompasses (a) a upper switching element having a first semiconductor chip, a first top electrode disposed at a top surface of the first semiconductor chip, a first bottom electrode disposed at a bottom surface of the first semiconductor chip, and a first control electrode configured to control conduction between the first top and first bottom electrodes; (b) a first wiring plate disposed beneath the upper switching element, electrically connected to the first bottom electrode; and (c) a lower switching element disposed beneath the wiring plate, having a second semiconductor chip, a second top electrode disposed at a top surface of the second semiconductor chip, electrically connected to the first wiring plate, a second bottom electrode disposed at a bottom surface of the second semiconductor chip, and a second control electrode configured to control conduction between the second top and second bottom electrodes.
摘要翻译：叠层半导体模块包括（a）具有第一半导体芯片的上开关元件，设置在第一半导体芯片的顶表面的第一顶电极，设置在第一半导体芯片的底表面处的第一底电极，以及第一控制电极，被配置为控制第一顶部电极和第一底部电极之间的导通; （b）设置在所述上开关元件下方的电连接到所述第一底电极的第一布线板; 以及（c）设置在所述布线板下方的下开关元件，具有第二半导体芯片，设置在所述第二半导体芯片的顶表面处的第二上电极，电连接到所述第一布线板，第二半导体芯片的底面以及第二控制电极，被配置为控制第二顶电极和第二底电极之间的导通。

78. 发明授权

US08923668B2 Receiving method and separating apparatus for light outputted from multi-core optical fiber 有权
标题翻译：从多芯光纤输出的光的接收方法和分离装置
公开(公告)号：US08923668B2
公开(公告)日：2014-12-30
申请号：US13401963
申请日：2012-02-22
申请人： Tetsuya Hayashi , Osamu Shimakawa
发明人： Tetsuya Hayashi , Osamu Shimakawa
IPC分类号： G02B6/36 , G02B6/26 , G01M11/00 , G01M11/08 , G02B6/036 , G02B6/02
CPC分类号： G02B6/262 , G01M11/088 , G01M11/33 , G02B6/02042 , G02B6/03683 , G02B6/3652 , G02B6/403
摘要： According to the present invention, as a result of using a depressed or trench-assisted light-receiving waveguide in which the core is surrounded by a layer having a refractive index lower than that of a cladding as light-receiving means for receiving light outputted from a multi-core optical fiber, the layer of a low refractive index can inhibit the propagation of noise, etc. from the cladding to the core. Consequently, even in cases where the inter-core crosstalk is small, it is possible to accurately measure the inter-core crosstalk since components different from crosstalk-derived components in optical power are reduced.
摘要翻译：根据本发明，作为使用凹陷或沟槽辅助的光接收波导的结果，其中芯被折射率低于包层折射率的层包围，作为用于接收从包层输出的光的光接收装置多芯光纤，低折射率层可以抑制噪声等从包层到芯的传播。因此，即使在芯间串扰小的情况下，也可以精确地测量芯间串扰，因为与光功率中的串扰导出分量不同的组件减少。

79. 发明申请

US20130094825A1 OPTICAL FIBER, OPTICAL FIBER CORD, AND OPTICAL FIBER CABLE 有权
标题翻译：光纤，光纤线和光纤电缆
公开(公告)号：US20130094825A1
公开(公告)日：2013-04-18
申请号：US13805465
申请日：2012-03-19
申请人： Tatsuya Konishi , Tetsuya Nakanishi , Tetsuya Hayashi
发明人： Tatsuya Konishi , Tetsuya Nakanishi , Tetsuya Hayashi
IPC分类号： G02B6/036
CPC分类号： G02B6/03638 , G02B6/0365
摘要： A trench optical fiber that stably realizes a small transmission loss includes (1) a core extending in an axial direction while containing an axial center of the fiber, the core having a diameter d1 of 7.0 μm to 7.4 μm; (2) a first optical cladding layer surrounding the core and having an outside diameter d2 of 1.67 dl to 2.5 dl; (3) a second optical cladding layer surrounding the first optical cladding layer; and (4) a jacket layer surrounding the second optical cladding layer and containing fluorine having a concentration of 0.06 wt % or higher. A relative refractive index difference Δ1 of the core with respect to the jacket layer is 0.31% to 0.37%. A relative refractive index difference Δ2 of the first optical cladding layer with respect to the jacket layer is +0.02% or larger and smaller than Δ1. A relative refractive index difference Δ3 of the second optical cladding layer with respect to the jacket layer is −0.2% or smaller.
摘要翻译：稳定地实现小的传输损耗的沟槽光纤包括：（1）沿轴向延伸的芯，同时包含纤维的轴向中心，芯的直径d1为7.0μm至7.4μm; （2）包围芯的第一光学包层，外径d2为1.67dl至2.5dl; （3）围绕所述第一光学包层的第二光学包层; 和（4）围绕第二光学包层并且含有浓度为0.06重量％以上的氟的护套层。芯相对于护套层的相对折射率差Δ1为0.31％至0.37％。第一光学包层相对于护套层的相对折射率差Δ2为+ 0.02％以上且小于Delta1。第二光学包覆层相对于护套层的相对折射率差Δ3为-0.2％以下。

80. 发明授权

US08400896B2 Information recording and reproducing apparatus, program for controlling same, computer-readable storage medium, method for controlling information recording and reproducing apparatus, and information storage medium 失效
标题翻译：信息记录和再现装置，用于控制其的程序，计算机可读存储介质，用于控制信息记录和再现装置的方法以及信息存储介质
公开(公告)号：US08400896B2
公开(公告)日：2013-03-19
申请号：US13138519
申请日：2010-02-22
申请人： Atsushi Etoh , Tetsuya Okumura , Hideharu Tajima , Shigemi Maeda , Yoshihisa Adachi , Tetsuya Hayashi , Yasuhiro Harada , Takashi Arimoto , Ikuo Nakano , Masaki Yamamoto , Hirohisa Yamada
发明人： Atsushi Etoh , Tetsuya Okumura , Hideharu Tajima , Shigemi Maeda , Yoshihisa Adachi , Tetsuya Hayashi , Yasuhiro Harada , Takashi Arimoto , Ikuo Nakano , Masaki Yamamoto , Hirohisa Yamada
IPC分类号： G11B15/04
CPC分类号： G11B7/00736 , G11B7/08511 , G11B7/24038 , G11B19/127 , G11B2007/0013 , G11B2220/235
摘要： An invention disclosed includes a layer number obtaining section (222) for determining which information storage layer (L1) has been accessed and a layer type identifying section (223) for identifying a type of the information storage layer (L1) determined by the layer number obtaining section (222). With the configuration, even in a case where an information recording and reproducing apparatus accesses an information storage layer different from an intended information storage layer by false operation or the like, it is still possible to dissolve mismatching between a recording or reproduction control scheme being set up and a recording or reproduction control scheme suitable for the information storage layer thus accessed.
摘要翻译：所公开的发明包括用于确定已经访问了哪个信息存储层（L1）的层号获取部分（222）和用于识别由层号确定的信息存储层（L1）的类型的层类型识别部分（223）获取部分（222）。利用这种配置，即使在信息记录和再现装置通过错误操作等访问与预期信息存储层不同的信息存储层的情况下，仍然可以解决设置的记录或再现控制方案之间的不匹配以及适合于如此访问的信息存储层的记录或再现控制方案。

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