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71. 发明申请

US20080223724A1 APPARATUSES FOR ELECTROCHEMICAL DEPOSITION, CONDUCTIVE LAYER, AND FABRICATION METHODS THEREOF 有权
标题翻译：电化学沉积装置，导电层及其制造方法
公开(公告)号：US20080223724A1
公开(公告)日：2008-09-18
申请号：US11686504
申请日：2007-03-15
申请人： Kei-Wei Chen , Mu-Han Cheng , Jian-Sin Tsai , Ying-Lang Wang
发明人： Kei-Wei Chen , Mu-Han Cheng , Jian-Sin Tsai , Ying-Lang Wang
IPC分类号： C25D9/00
CPC分类号： C25D17/001 , C25D17/007 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76877 , Y10T428/16
摘要： Electrochemical plating (ECP) apparatuses with auxiliary cathodes to create uniform electric flux density. An ECP apparatus for electrochemical deposition includes an electrochemical cell with an electrolyte bath for electrochemically depositing a metal on a substrate. A main cathode and an anode are disposed in the electrolyte bath to provide a main electrical field. A substrate holder assembly holds a semiconductor wafer connecting the cathode. An auxiliary cathode is disposed outside the electrochemical cell to provide an auxiliary electrical field such that a flux line density at the center region of the substrate holder assembly substantially equals that at the circumference of the substrate holder assembly.
摘要翻译：具有辅助阴极的电化学电镀（ECP）装置，以产生均匀的电流密度。用于电化学沉积的ECP设备包括具有用于在基底上电化学沉积金属的电解质浴的电化学电池。主阴极和阳极设置在电解槽中以提供主电场。衬底保持器组件保持连接阴极的半导体晶片。辅助阴极设置在电化学电池外部以提供辅助电场，使得衬底保持器组件的中心区域处的磁通线密度基本上等于衬底保持器组件的圆周处的磁通密度。

72. 发明申请

US20080061343A1 Metal-oxide-metal structure with improved capacitive coupling area 审中-公开
标题翻译：具有改善电容耦合面积的金属氧化物 - 金属结构
公开(公告)号：US20080061343A1
公开(公告)日：2008-03-13
申请号：US11518470
申请日：2006-09-08
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.
摘要翻译：一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。

73. 发明申请

US20070252277A1 SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070252277A1
公开(公告)日：2007-11-01
申请号：US11380666
申请日：2006-04-28
申请人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer filled into the opening. The invention also provides a method of fabricating the semiconductor device.
摘要翻译：半导体器件。所述半导体器件包括：衬底，形成在其上的电介质层，形成在所述电介质层中的开口;覆盖所述开口侧壁的第一阻挡层，覆盖所述第一阻挡层和所述开口底部的第二势垒层;以及导电层填充入开口。本发明还提供一种制造半导体器件的方法。

74. 发明申请

US20070084730A1 Plating apparatuses and processes 审中-公开
标题翻译：电镀设备和工艺
公开(公告)号：US20070084730A1
公开(公告)日：2007-04-19
申请号：US11248176
申请日：2005-10-13
申请人： Kei-Wei Chen , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： C25D5/48
CPC分类号： C25D21/00 , C25D5/00 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76877 , H05K3/423
摘要： Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.
摘要翻译：电镀设备和电镀工艺。电镀装置包括电镀站和邻近电镀站的电镀后处理站。电镀站包括至少一个电镀槽，并在其中提供第一相对湿度（RH）高于设置有电镀设备的洁净室的第一相对湿度（RH）。后电镀处理站在其中提供第二环境，其第二RH低于第一RH。

75. 发明授权

US07071100B2 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US07071100B2
公开(公告)日：2006-07-04
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

76. 发明申请

US20050250327A1 Copper plating of semiconductor devices using intermediate immersion step 有权
标题翻译：使用中间浸渍步骤的半导体器件的镀铜
公开(公告)号：US20050250327A1
公开(公告)日：2005-11-10
申请号：US10840095
申请日：2004-05-06
申请人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
发明人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
IPC分类号： C25D3/02 , C25D5/10 , C25D5/18 , C25D7/12 , H01L21/288 , H01L21/44
CPC分类号： C25D7/123 , C25D3/02 , C25D5/10 , C25D5/18 , H01L21/2885
摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.
摘要翻译：在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

77. 发明申请

US20050191855A1 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US20050191855A1
公开(公告)日：2005-09-01
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

78. 发明申请

US20050133059A1 Method for cleaning a plasma enhanced CVD chamber 有权
标题翻译：清洁等离子体增强CVD室的方法
公开(公告)号：US20050133059A1
公开(公告)日：2005-06-23
申请号：US10738740
申请日：2003-12-17
申请人： Sheng-Wen Chen , Shiu-Ko Jangjian , Hung-Jui Chang , Ying-Lang Wang
发明人： Sheng-Wen Chen , Shiu-Ko Jangjian , Hung-Jui Chang , Ying-Lang Wang
IPC分类号： B08B6/00 , B08B7/00 , C23C16/44 , H01L21/00 , H01L21/30 , H01L21/3065
CPC分类号： C23C16/4405 , B08B7/00 , H01L21/67069 , Y10S134/902 , Y10S438/905
摘要： A method for plasma cleaning a CVD reactor chamber including providing a plasma enhanced CVD reactor chamber comprising residual deposited material; performing a first plasma process comprising an oxygen containing plasma; performing a second plasma process comprising an argon containing plasma; and, performing a third plasma process comprising a fluorine containing plasma.
摘要翻译：一种用于等离子体清洗CVD反应器室的方法，包括提供包含残余沉积材料的等离子体增强CVD反应器室; 执行包含含氧等离子体的第一等离子体工艺; 执行包括含氩等离子体的第二等离子体工艺; 以及执行包括含氟等离子体的第三等离子体工艺。

79. 发明申请

US20050056544A1 Dual contact ring and method for metal ECP process 有权
标题翻译：双接触环和金属ECP工艺方法
公开(公告)号：US20050056544A1
公开(公告)日：2005-03-17
申请号：US10664347
申请日：2003-09-16
申请人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
IPC分类号： C25D5/02 , C25D5/48 , B23H7/26
CPC分类号： C25D5/48 , C25D5/028 , Y10S204/07
摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
摘要翻译：用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。外部电压环连接到正电压源，内部电压环连接到负电压源。内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

80. 发明授权

US06531382B1 Use of a capping layer to reduce particle evolution during sputter pre-clean procedures 有权
标题翻译：在溅射预清洁过程中使用覆盖层来减少颗粒的发生
公开(公告)号：US06531382B1
公开(公告)日：2003-03-11
申请号：US10140662
申请日：2002-05-08
申请人： Tao Cheng , Wen-Hsin Huang , Jiun-Pyng You , Lin-June Wu , Shih-Tzung Chang , Ming-Jei Lee , Chun-Chang Chen , Yu-Ku Lin , Tong-Hua Kuan , Ying-Lang Wang
发明人： Tao Cheng , Wen-Hsin Huang , Jiun-Pyng You , Lin-June Wu , Shih-Tzung Chang , Ming-Jei Lee , Chun-Chang Chen , Yu-Ku Lin , Tong-Hua Kuan , Ying-Lang Wang
IPC分类号： H01L213205
CPC分类号： H01L21/76802 , H01L21/76838
摘要： A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer. An in situ metal deposition then allows a clean interface to result between the overlying metal layer, and the underlying plasma treated, metal surface.
摘要翻译：已经开发了制备在亚微米直径开口的底部露出的下层金属结构的表面以允许在与上层金属结构重叠时获得低电阻界面的方法。首先将一次性封盖绝缘体层沉积在复合绝缘体层上，在该复合绝缘层上将限定亚微米直径的开口，以保护复合绝缘子的下面的部件免于后续的金属预金属工艺。在各向异性地限定封盖绝缘体中的亚微米直径开口和复合绝缘体层之后，并且在去除限定的光致抗蚀剂形状之后，使用氩溅射方法从下层金属结构的表面去除自然氧化物。除了自然氧化物除去之外，具有施加到衬底的负DC偏压的氩溅射工艺也从复合绝缘体层的顶表面去除封盖绝缘体层。原位金属沉积然后允许在上覆的金属层和下面的等离子体处理的金属表面之间产生干净的界面。

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