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1. 发明申请

US20050056544A1 Dual contact ring and method for metal ECP process 有权
标题翻译：双接触环和金属ECP工艺方法
公开(公告)号：US20050056544A1
公开(公告)日：2005-03-17
申请号：US10664347
申请日：2003-09-16
申请人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
IPC分类号： C25D5/02 , C25D5/48 , B23H7/26
CPC分类号： C25D5/48 , C25D5/028 , Y10S204/07
摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
摘要翻译：用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。外部电压环连接到正电压源，内部电压环连接到负电压源。内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

2. 发明授权

US07252750B2 Dual contact ring and method for metal ECP process 有权
标题翻译：双接触环和金属ECP工艺方法
公开(公告)号：US07252750B2
公开(公告)日：2007-08-07
申请号：US10664347
申请日：2003-09-16
申请人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
IPC分类号： C25D17/00
CPC分类号： C25D5/48 , C25D5/028 , Y10S204/07
摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
摘要翻译：用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。外部电压环连接到正电压源，内部电压环连接到负电压源。内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

3. 发明申请

US20050275941A1 Metal-filled openings for submicron devices and methods of manufacture thereof 有权
标题翻译：用于亚微米器件的金属填充开口及其制造方法
公开(公告)号：US20050275941A1
公开(公告)日：2005-12-15
申请号：US10854061
申请日：2004-05-26
申请人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
发明人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
IPC分类号： G02B23/00 , H01L21/768 , H01L21/82
CPC分类号： H01L21/7684 , H01L21/76877
摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.
摘要翻译：在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

4. 发明授权

US07071100B2 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US07071100B2
公开(公告)日：2006-07-04
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

5. 发明申请

US20050191855A1 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US20050191855A1
公开(公告)日：2005-09-01
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

6. 发明授权

US08247322B2 Via/contact and damascene structures and manufacturing methods thereof 有权
标题翻译：通孔/接触和镶嵌结构及其制造方法
公开(公告)号：US08247322B2
公开(公告)日：2012-08-21
申请号：US11680981
申请日：2007-03-01
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
摘要翻译：形成半导体结构的方法包括在衬底上形成电介质层。在电介质层上形成第一非导电阻挡层。通过第一非导电阻挡层和介电层内形成至少一个开口。在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上的开幕。然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

7. 发明授权

US08552529B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08552529B2
公开(公告)日：2013-10-08
申请号：US13488958
申请日：2012-06-05
申请人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
发明人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.
摘要翻译：公开了一种半导体器件。该装置包括基板; 覆盖衬底的第一金属层; 覆盖在第一金属层上的电介质层; 以及覆盖所述电介质层的第二金属层，其中所述第一金属层包括：第一体心立方晶格金属层; 第一底层，位于第一体心立方晶格金属层下面，其中第一底层是体心立方晶格的金属，包括钛（Ti），钨（W），钼（Mo）或铌（Nb）; 以及在第一体心立方晶格金属层和第一底层之间的体心立方晶格的第一界面。

8. 发明申请

US20080211106A1 VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF 有权
标题翻译：威盛/联系人和丹麦结构及其制造方法
公开(公告)号：US20080211106A1
公开(公告)日：2008-09-04
申请号：US11680981
申请日：2007-03-01
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
摘要翻译：形成半导体结构的方法包括在衬底上形成电介质层。在电介质层上形成第一非导电阻挡层。通过第一非导电阻挡层和介电层内形成至少一个开口。在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上的开幕。然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

9. 发明申请

US20070252277A1 SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070252277A1
公开(公告)日：2007-11-01
申请号：US11380666
申请日：2006-04-28
申请人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer filled into the opening. The invention also provides a method of fabricating the semiconductor device.
摘要翻译：半导体器件。所述半导体器件包括：衬底，形成在其上的电介质层，形成在所述电介质层中的开口;覆盖所述开口侧壁的第一阻挡层，覆盖所述第一阻挡层和所述开口底部的第二势垒层;以及导电层填充入开口。本发明还提供一种制造半导体器件的方法。

10. 发明授权

US08531036B2 Via/contact and damascene structures 有权
标题翻译：通过/接触和镶嵌结构
公开(公告)号：US08531036B2
公开(公告)日：2013-09-10
申请号：US13563495
申请日：2012-07-31
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
IPC分类号： H01L23/48
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.
摘要翻译：提供半导体结构，并且包括设置在基板上的电介质层。在电介质层上形成第一非导电阻挡层。通过第一非导电阻挡层和介电层内形成至少一个开口。在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上的开幕。种子层和导电层设置在开口中。

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