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71. 再颁专利

USRE37552E1 System and method for power-efficient charging and discharging of a capacitive load from a single source 失效
标题翻译：从单个电源对电容性负载进行高效充电和放电的系统和方法
公开(公告)号：USRE37552E1
公开(公告)日：2002-02-19
申请号：US08986327
申请日：1997-12-05
申请人： Lars Svensson , William C. Athas , Jeffrey G. Koller
发明人： Lars Svensson , William C. Athas , Jeffrey G. Koller
IPC分类号： H02M307
CPC分类号： G05F1/565 , H02M3/07 , H02M3/158
摘要： A system and method for efficiently charging and discharging a capacitive load from a single voltage source. The system includes a first switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may be common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged. In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.
摘要翻译：一种用于从单个电压源高效地对容性负载进行充电和放电的系统和方法。该系统包括用于选择性地将电压源连接到负载的第一开关和用于选择性地跨越负载提供短路的第二开关，如本领域常见的那样。本发明的特别新颖的方面在于提供多个电容元件和用于选择性地将每个电容元件连接到负载的开关机构，由此负载逐渐充电或放电。在说明性实施例中，切换机构包括用于选择性地将每个电容元件连接到电容性负载的开关组以及用于选择性地启动开关的开关控制机构。

72. 发明授权

US5047917A Apparatus for intrasystem communications within a binary n-cube including buffer lock bit 失效
标题翻译：用于在包括缓冲锁定位的二进制n-cube内进行系统间通信的装置
公开(公告)号：US5047917A
公开(公告)日：1991-09-10
申请号：US303977
申请日：1989-01-31
申请人： William C. Athas , Reese Faucette , Charles L. Seitz
发明人： William C. Athas , Reese Faucette , Charles L. Seitz
IPC分类号： G06F15/173
CPC分类号： G06F15/17343
摘要： An improved communication system for the prevention of lockup in a computer system of the binary n-cube type. Input circuitry at each of the nodes is connected for receiving messages and includes an input buffer for initially receiving the messages. Output circuitry at each of the nodes is connected for transmitting holding the messages prior to and during transmission thereof. A kernel program at each of the nodes acts as an interface between the user process programs and exclusively controls the receiving and transmitting of messages into and out of the node. There is provision for the user process programs to pass control to the kernel program to request the sending and receiving of messages by the kernel program. A lock bit is associated with each message, sensible by the user process programs, and reset by the kernel program when the kernel program has transferred the associated message. Asynchronous transfer circuitry independently and asynchronously transfers the messages as packets between the buffers of the nodes. There is logic for various decisional matters regarding message sending and receipt. There is blockout prevention logic for refusing to receive a message unless a user process program in the node has reserved a buffer of sufficient size to receive the message and for listing messages waiting to be received for which space has not yet been reserved.
摘要翻译：一种改进的通信系统，用于防止二进制n型立方体类型的计算机系统中的锁定。每个节点处的输入电路被连接用于接收消息，并且包括用于初始接收消息的输入缓冲器。在每个节点处的输出电路被连接用于发送之前和期间的发送。每个节点上的内核程序用作用户进程程序之间的接口，并专门控制消息的接收和发送进出节点。用户进程程序提供了向内核程序传递控制权以请求内核程序发送和接收消息的规定。锁定位与每个消息相关联，由用户进程程序显示，并且当内核程序传送关联的消息时由内核程序重置锁定位。异步传输电路独立且异步地将消息作为数据包传输到节点的缓冲区之间。有关消息发送和接收的各种决定事项的逻辑。除非节点中的用户处理程序已经预留了足够大小的缓冲区以接收消息并列出等待接收的空间尚未被保留的消息，否则存在用于拒绝接收消息的防止阻止逻辑。

73. 发明申请

US20130335149A1 THE EFFICIENCY OF CLIPPED PULSE GENERATION 有权
标题翻译：剪切脉冲发生的效率
公开(公告)号：US20130335149A1
公开(公告)日：2013-12-19
申请号：US13527477
申请日：2012-06-19
申请人： William C. Athas , Catherine S. Chou
发明人： William C. Athas , Catherine S. Chou
IPC分类号： H03L9/00
CPC分类号： H03B5/1234 , H03B5/1212 , H03B5/1228
摘要： The disclosed embodiments provide a resonant oscillator circuit. The resonant oscillator circuit includes a clipping mechanism configured to clip an output voltage of a signal pulse generated by the resonant oscillator circuit to a predefined constant level. The resonant oscillator circuit also includes a feedback path configured to return energy from the clipping mechanism to an input of the resonant oscillator circuit.
摘要翻译：所公开的实施例提供了一种谐振振荡器电路。谐振振荡器电路包括限幅机构，其构造成将由共振振荡器电路产生的信号脉冲的输出电压钳位到预定的恒定电平。谐振振荡器电路还包括被配置为将能量从限幅机构返回到谐振振荡器电路的输入的反馈路径。

74. 发明授权

US08412105B2 Electronic devices with radio-frequency collision resolution capabilities 有权
公开(公告)号：US08412105B2
公开(公告)日：2013-04-02
申请号：US11986892
申请日：2007-11-26
申请人： John Gregory Dorsey , William C. Athas
发明人： John Gregory Dorsey , William C. Athas
IPC分类号： H04B15/00
CPC分类号： H04B15/04 , H04B15/02
摘要： Electronic devices such as portable electronic devices contain electronic components. The electronic components may include radio-frequency transceiver circuitry. The radio-frequency transceiver circuitry may be used for handling data communications and cellular telephone voice communications. One or more adjustable clock sources may be provided within the electronic device. The adjustable clock sources may be based on phase-locked-loop circuits. A clock manager may determine which frequencies are being used by the radio-frequency transceiver circuitry and other components in the electronic device. The clock manager may use this information to compute a list of safe fundamental clock signal frequencies. Based on the list of safe clock signal frequencies, the clock manager may dynamically adjust the clock sources to avoid collisions between harmonics of the clock signals from the clock sources and the frequencies used by the transceiver circuitry and other components.

75. 发明授权

US08244296B2 Dynamic thermal control for wireless transceivers 有权
公开(公告)号：US08244296B2
公开(公告)日：2012-08-14
申请号：US12288027
申请日：2008-10-15
申请人： John G. Dorsey , William C. Athas
发明人： John G. Dorsey , William C. Athas
IPC分类号： H04M1/00
CPC分类号： H04W52/0251 , H04B1/036 , Y02D70/00 , Y02D70/1224 , Y02D70/1242 , Y02D70/1244 , Y02D70/1246 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/22 , Y02D70/40
摘要： Methods and apparatus for dynamic thermal management and control within, e.g., small form-factor wireless devices such as laptop computers or cellular “smartphones”. In one embodiment, a thermal management system monitors the temperature (or other relevant criteria) for one or more components, and implements different operating states within the wireless transceiver (e.g., Wi-Fi™ or WiMAX transceiver) so as to both reduce thermal output and minimize disruption to the wireless link and/or user experience. In another embodiment, a wireless client may communicate with other clients, and/or access points, so as to cooperatively provide more options for thermal management. In addition, methods and apparatus employing “high performance” (e.g., high power output or high data rate) radios within aggressively small industrial designs are also disclosed.

76. 发明申请

US20110032043A1 RESONANT OSCILLATOR CIRCUIT WITH REDUCED STARTUP TRANSIENTS 有权
标题翻译：具有减少启动瞬态的谐振器振荡器电路
公开(公告)号：US20110032043A1
公开(公告)日：2011-02-10
申请号：US12629370
申请日：2009-12-02
申请人： William C. Athas
发明人： William C. Athas
IPC分类号： H03B5/12
CPC分类号： H02M3/07 , H03B5/06 , H03B5/1212 , H03B5/1228 , H03B2200/0094 , H03B2200/0096
摘要： Some embodiments of the present invention provide a system that implements a resonant oscillator circuit. This resonant oscillator circuit includes: a first inductor, a second inductor, a first capacitance, and a second capacitance, wherein the first and second inductors are configured to operate with the first and second capacitances to produce resonant oscillations which appear at a first phase output and a second phase output. The system also includes a startup circuit which is configured to start the resonant oscillator circuit in a state where: the first phase output is at a peak voltage; the second phase output is at a base voltage; and currents through the first and second inductors are substantially zero. By starting the resonant oscillator circuit in this state, the oscillations commence without a significant startup transient.
摘要翻译：本发明的一些实施例提供一种实现谐振振荡器电路的系统。该谐振振荡器电路包括：第一电感器，第二电感器，第一电容器和第二电容器，其中第一和第二电感器被配置为与第一和第二电容器一起工作，以产生出现在第一相位输出和第二相输出。该系统还包括启动电路，其被配置为在第一相输出处于峰值电压的状态下启动谐振振荡器电路; 第二相输出为基极电压; 并且通过第一和第二电感器的电流基本上为零。通过在该状态下启动谐振振荡器电路，振荡开始而没有明显的启动瞬变。

77. 发明申请

US20110032042A1 RESONANT OSCILLATOR WITH OSCILLATION-STARTUP CIRCUITRY 有权
标题翻译：具振荡启动电路的谐振器
公开(公告)号：US20110032042A1
公开(公告)日：2011-02-10
申请号：US12540578
申请日：2009-08-13
申请人： William C. Athas
发明人： William C. Athas
IPC分类号： H03B5/12
CPC分类号： H02M3/07 , H03B5/06 , H03B5/1212 , H03B5/1228 , H03B2200/0094 , H03B2200/0096
摘要： Some embodiments of the present invention provide a system that implements a resonant oscillator circuit. This system includes a first inductor with a constant potential terminal coupled to an input voltage, and a time-varying potential terminal coupled to a first phase output. The system also includes a second inductor with a constant potential terminal coupled to the input voltage, and a time-varying potential terminal coupled to a second phase output. The system additionally includes a first n-type transistor with a source terminal coupled to a base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output. The system also includes a second n-type transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output. Finally, the system includes a startup circuit configured to commence oscillations in the resonant oscillator circuit by energizing the first inductor before energizing the second inductor.
摘要翻译：本发明的一些实施例提供一种实现谐振振荡器电路的系统。该系统包括具有耦合到输入电压的恒定电位端的第一电感器和耦合到第一相输出的时变电位端子。该系统还包括具有耦合到输入电压的恒定电位端子的第二电感器和耦合到第二相输出端的时变电位端子。该系统还包括具有耦合到基极电压的源极端子的第一n型晶体管，耦合到第一相位输出的漏极端子和耦合到第二相位输出的栅极端子。该系统还包括具有耦合到基极电压的源极端子的第二n型晶体管，耦合到第二相位输出的漏极端子和耦合到第一相位输出的栅极端子。最后，该系统包括启动电路，该启动电路经配置以在激励第二电感器之前激励第一电感器来开始谐振振荡器电路中的振荡。

78. 发明申请

US20110031956A1 HIGH-EFFICIENCY, SWITCHED-CAPACITOR POWER CONVERSION 有权
标题翻译：高效率，开关电容转换
公开(公告)号：US20110031956A1
公开(公告)日：2011-02-10
申请号：US12535974
申请日：2009-08-05
申请人： William C. Athas , P. Jeffrey Ungar
发明人： William C. Athas , P. Jeffrey Ungar
IPC分类号： H02M3/00
CPC分类号： H02M3/07
摘要： Some embodiments of the present invention provide a system that efficiently converts between a lower input voltage and a higher output voltage. This system includes an input which receives the input voltage, and an output which provides the output voltage. The system also includes a first capacitor with a higher potential terminal and a lower potential terminal, as well as a first set of switching devices which selectively couple the higher potential and lower potential terminals of the first capacitor between the input voltage, the output voltage and a base voltage. The system additionally includes a resonant clocking circuit which generates clock signals with substantially non-overlapping clock phases, including a first phase and a second phase. This resonant clocking circuit is configured to control the first set of switching devices so that during the first phase, the higher potential terminal of the first capacitor is coupled to the input voltage and the lower potential terminal of the first capacitor is coupled to the base voltage, and during the second phase, the higher potential terminal of the first capacitor is coupled to the output voltage and the lower potential terminal of the first capacitor is coupled to the input voltage.
摘要翻译：本发明的一些实施例提供一种能够在较低输入电压和较高输出电压之间有效转换的系统。该系统包括接收输入电压的输入和提供输出电压的输出。该系统还包括具有较高电位端子和较低电位端子的第一电容器以及第一组开关器件，其选择性地将第一电容器的较高电位和低电位端子耦合在输入电压，输出电压和基极电压。该系统还包括谐振时钟电路，其产生具有基本上非重叠时钟相位的时钟信号，包括第一相位和第二相位。该谐振时钟电路被配置为控制第一组开关器件，使得在第一相期间，第一电容器的较高电位端子耦合到输入电压，并且第一电容器的下电位端子耦合到基极电压并且在第二阶段期间，第一电容器的较高电位端耦合到输出电压，并且第一电容器的下电位端耦合到输入电压。

79. 发明授权

US07872539B1 Energy efficient waveform generation using tuned resonators 有权
标题翻译：使用调谐谐振器的能量效率波形生成
公开(公告)号：US07872539B1
公开(公告)日：2011-01-18
申请号：US12861657
申请日：2010-08-23
申请人： William C. Athas
发明人： William C. Athas
IPC分类号： H03B11/04 , H03B11/10
CPC分类号： H03L7/099 , H03B5/1203 , H03B5/1212 , H03B5/1221 , H03B5/1228
摘要： A power source, a primary inductor, a load capacitance, and one or more tuned branch resonators and switching devices are coupled to generate pulses which represent a superposition of sinusoidal waveforms. The primary inductor is connected between the power source and the load. At the start of each cycle the load is coupled to ground and each tuned-branch resonators is reinitialized to re-energize the circuits and to stabilize the waveform when the frequencies of the sinusoidal waveforms are non-periodic.
摘要翻译：电源，初级电感器，负载电容以及一个或多个调谐分支谐振器和开关器件被耦合以产生表示正弦波形叠加的脉冲。主电感连接在电源和负载之间。在每个周期的开始，负载被耦合到地，并且每个调谐支路谐振器被重新初始化以重新激励电路，并且当正弦波形的频率是非周期性时稳定波形。

80. 发明授权

US07558947B1 Method and apparatus for computing vector absolute differences 有权
标题翻译：用于计算矢量绝对差的方法和装置
公开(公告)号：US07558947B1
公开(公告)日：2009-07-07
申请号：US10038431
申请日：2001-12-31
申请人： Sushma Shrikant Trivedi , Joseph P. Bratt , Vaughn Todd Arnold , William C. Athas , Jason Chen
发明人： Sushma Shrikant Trivedi , Joseph P. Bratt , Vaughn Todd Arnold , William C. Athas , Jason Chen
IPC分类号： G06F7/38
CPC分类号： G06F7/544 , G06F2207/5442
摘要： Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a first plurality of numbers and a second plurality of numbers; and generating simultaneously a third plurality of numbers, each of which is an absolute difference between a number in the first plurality of numbers and a number in the second plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.
摘要翻译：用于计算两个数字向量的绝对差的方法和装置。在本发明的一个方面中，微处理器响应于接收单个指令而执行的方法包括：接收第一多个数字和第二多个数字; 并且同时产生第三多个数字，每个数字是第一多个数字中的数字和第二个多个数字中的数字之间的绝对差。响应于微处理器接收到单个指令执行上述操作。

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