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71. 发明授权

US07586778B2 Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states 有权
标题翻译：操作具有多个存储器层和多级存储器状态的双稳态电阻随机存取存储器的方法
公开(公告)号：US07586778B2
公开(公告)日：2009-09-08
申请号：US12134117
申请日：2008-06-05
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： G11C11/00
CPC分类号： G11C17/165 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C17/16 , G11C2213/31 , G11C2213/32 , G11C2213/77
摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.
摘要翻译：描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。四个不同逻辑状态之间的关系可以用两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R 逻辑“1”状态由数学表达式（n + f）R表示。逻辑“2”状态由数学表达式（1 + nf）R表示。逻辑“3”状态由数学表达式n（1 + f）R

72. 发明授权

US07531825B2 Method for forming self-aligned thermal isolation cell for a variable resistance memory array 有权
标题翻译：用于形成用于可变电阻存储器阵列的自对准热隔离单元的方法
公开(公告)号：US07531825B2
公开(公告)日：2009-05-12
申请号：US11463824
申请日：2006-08-10
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L47/00 , G11C11/56
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1683
摘要： A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element and the lower electrode element, and this element includes a sidewall spacer element having an inner surface defining a generally funnel-shaped central cavity, terminating at a terminal edge to define a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode, having an inner surface defining a thermal isolation cell, the spandrel inner walls being spaced radially outward from the sidewall spacer terminal edge, such that the sidewall spacer terminal edge projects radially inward from the spandrel element inner surface. ARRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.
摘要翻译：具有自对准RRAM元素的非易失性方法。该方法包括具有内部接触表面的大体平面形状的下部电极元件。在装置的顶部是与下部电极元件间隔开的上部电极元件。容纳结构在上电极元件和下电极元件之间延伸，并且该元件包括侧壁间隔元件，其具有限定大致漏斗形中心腔的内表面，终止于端边缘以限定中心孔; 以及位于所述侧壁间隔元件和所述下电极之间的突出元件，具有限定了热隔离单元的内表面，所述凸起内壁与所述侧壁间隔件终端边缘径向向外间隔开，使得所述侧壁间隔件末端边缘径向向内突出从弹簧元件内表面。 ARRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔元件中心空腔的至少一部分并且从侧壁间隔件终端边缘朝向和与下电极接触。以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

73. 发明申请

US20090057748A1 Memory and manufacturing method thereof 有权
标题翻译：其记忆及其制造方法
公开(公告)号：US20090057748A1
公开(公告)日：2009-03-05
申请号：US11892980
申请日：2007-08-29
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/788 , H01L21/8239
CPC分类号： H01L29/792 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578
摘要： A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure.
摘要翻译：提供了一种存储器及其制造方法。存储器包括电介质层，多晶硅层，第一掩埋扩散层，第二掩埋扩散层，电荷存储结构和栅极。多晶硅层设置在电介质层上并电连接至少一个电压。第一掩埋扩散部和第二掩埋扩散部分别设置在多晶硅层的表面。电荷存储结构设置在多晶硅层上并且位于第一掩埋扩散区和第二掩埋扩散区之间。栅极设置在电荷存储结构上。

74. 发明申请

US20090020746A1 SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY 有权
标题翻译：自对准结构和方法，用于在电阻随机访问存储器中配置熔点
公开(公告)号：US20090020746A1
公开(公告)日：2009-01-22
申请号：US12235773
申请日：2008-09-23
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

75. 发明授权

US07414282B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07414282B2
公开(公告)日：2008-08-19
申请号：US11203087
申请日：2005-08-15
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

76. 发明申请

US20080173982A1 Resistance random access memory 有权
标题翻译：电阻随机存取存储器
公开(公告)号：US20080173982A1
公开(公告)日：2008-07-24
申请号：US11656246
申请日：2007-01-18
申请人： Erh-Kun Lai , Chiahua Ho , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang-Yeu Hsieh
IPC分类号： H01L29/12
CPC分类号： H01L27/24 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C16/0475 , G11C2213/31 , G11C2213/51
摘要： A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.
摘要翻译：存储器包括在第一方向上的多个字线，第二方向上的多个位线，每个字线连接到至少一个字线，以及多个存储器元件，每个存储器元件耦合到字线之一，其中一个位线。每个存储元件包括用于连接到对应的字线的顶部电极，用于连接到对应的位线的底部电极，底部电极上的电阻层，以及至少两个分离的衬垫，每个衬垫在两端具有电阻材料衬垫和每个衬垫耦合在顶部电极和电阻层之间。

77. 发明申请

US20080121861A1 Self-Aligned Structure and Method for Confining a Melting Point in a Resistor Random Access Memory 有权
标题翻译：用于限制电阻随机存取存储器中的熔点的自对准结构和方法
公开(公告)号：US20080121861A1
公开(公告)日：2008-05-29
申请号：US11465094
申请日：2006-08-16
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

78. 发明申请

US20080089111A1 RESISTANCE TYPE MEMORY DEVICE AND FABRICATING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：电阻型存储器件及其制造方法及其工作方法
公开(公告)号：US20080089111A1
公开(公告)日：2008-04-17
申请号：US11695780
申请日：2007-04-03
申请人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C11/54 , G11C11/14 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633 , Y10S438/972
摘要： A resistance type memory device is provided. The resistance type memory device is disposed on a substrate and includes a tungsten electrode, an upper electrode, and a tungsten oxide layer. The upper electrode is disposed on the tungsten electrode. The tungsten oxide layer is sandwiched between the tungsten electrode and the upper electrode.
摘要翻译：提供电阻型存储器件。电阻型存储装置设置在基板上，并且包括钨电极，上电极和氧化钨层。上电极设置在钨电极上。氧化钨层夹在钨电极和上电极之间。

79. 发明授权

US08927956B2 Resistance type memory device 有权
标题翻译：电阻型记忆装置
公开(公告)号：US08927956B2
公开(公告)日：2015-01-06
申请号：US12403186
申请日：2009-03-12
申请人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L45/00 , G11C11/00 , G11C13/00 , G11C11/54 , G11C11/14 , G11C11/56
CPC分类号： G11C11/54 , G11C11/14 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633 , Y10S438/972
摘要： A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.
摘要翻译：提供电阻型存储器件。电阻型存储器件包括第一和第二导体和金属氧化物层。金属氧化物层设置在第一和第二导体之间，电阻型存储装置被定义为第一电阻率。在向金属氧化物层施加第一脉冲电压之后，将电阻型存储器件定义为第二电阻率。在向金属氧化物层施加第二脉冲电压之后，将电阻型存储器件定义为第三电阻率。第二电阻率大于第一电阻率，第一电阻率大于第三电阻率。

80. 发明授权

US08704205B2 Semiconductor structure with improved capacitance of bit line 有权
标题翻译：具有改善位线电容的半导体结构
公开(公告)号：US08704205B2
公开(公告)日：2014-04-22
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

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