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1. 发明授权

US08243494B2 Self-aligned structure and method for confining a melting point in a resistor random access memory 有权
标题翻译：用于将熔点限制在电阻随机存取存储器中的自对准结构和方法
公开(公告)号：US08243494B2
公开(公告)日：2012-08-14
申请号：US12235773
申请日：2008-09-23
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： G11C16/02 , H01L29/417
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

2. 发明授权

US07442603B2 Self-aligned structure and method for confining a melting point in a resistor random access memory 有权
标题翻译：用于将熔点限制在电阻随机存取存储器中的自对准结构和方法
公开(公告)号：US07442603B2
公开(公告)日：2008-10-28
申请号：US11465094
申请日：2006-08-16
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L27/13
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

3. 发明申请

US20090020746A1 SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY 有权
标题翻译：自对准结构和方法，用于在电阻随机访问存储器中配置熔点
公开(公告)号：US20090020746A1
公开(公告)日：2009-01-22
申请号：US12235773
申请日：2008-09-23
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

4. 发明申请

US20080121861A1 Self-Aligned Structure and Method for Confining a Melting Point in a Resistor Random Access Memory 有权
标题翻译：用于限制电阻随机存取存储器中的熔点的自对准结构和方法
公开(公告)号：US20080121861A1
公开(公告)日：2008-05-29
申请号：US11465094
申请日：2006-08-16
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

5. 发明授权

US08704205B2 Semiconductor structure with improved capacitance of bit line 有权
标题翻译：具有改善位线电容的半导体结构
公开(公告)号：US08704205B2
公开(公告)日：2014-04-22
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

6. 发明申请

US20140054535A1 SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
标题翻译：具有改进位线电容的半导体结构
公开(公告)号：US20140054535A1
公开(公告)日：2014-02-27
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

7. 发明授权

US08178405B2 Resistor random access memory cell device 有权
标题翻译：电阻随机存取存储单元器件
公开(公告)号：US08178405B2
公开(公告)日：2012-05-15
申请号：US12755897
申请日：2010-04-07
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/8242
CPC分类号： H01L45/122 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.
摘要翻译：存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件材料。因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

8. 发明授权

US08139393B2 Method and apparatus for non-volatile multi-bit memory 有权
标题翻译：用于非易失性多位存储器的方法和装置
公开(公告)号：US08139393B2
公开(公告)日：2012-03-20
申请号：US12576212
申请日：2009-10-08
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/79 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/144 , H01L45/146 , H01L45/1633
摘要： A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.
摘要翻译：可选择地显示第一和第二逻辑电平的存储器件。第一导电材料具有形成在其上的第一存储层的第一表面，并且第二导电材料具有形成在其上的第二存储层的第二表面。连接导电层连接第一和第二存储层并将其放置在电接触中。该结构被设计成使得第一存储层的横截面积小于第二存储层的横截面面积。

9. 发明授权

US07972893B2 Memory device manufacturing method 有权
标题翻译：存储器件制造方法
公开(公告)号：US07972893B2
公开(公告)日：2011-07-05
申请号：US12469184
申请日：2009-05-20
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang-Yeu Hsieh
IPC分类号： H01L21/00
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.
摘要翻译：制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。第一和第二电极形成在第一和第二表面上。存储元件形成在表面段上以电连接第一和第二电极。

10. 发明授权

US07923285B2 Method for forming self-aligned thermal isolation cell for a variable resistance memory array 有权
标题翻译：用于形成用于可变电阻存储器阵列的自对准热隔离单元的方法
公开(公告)号：US07923285B2
公开(公告)日：2011-04-12
申请号：US12351692
申请日：2009-01-09
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1683
摘要： A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.
摘要翻译：具有自对准RRAM元件的非易失性存储器包括具有内接触表面的大体平面形状的下电极元件; 与所述下电极元件间隔开的上电极元件; 容纳结构在上电极元件和下电极元件之间延伸，侧壁间隔元件具有大致漏斗形的具有中心孔的中心腔; 以及位于侧壁间隔元件和下电极之间的突出元件。 RRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔件元件中心腔的至少一部分并且从侧壁间隔件端子边缘朝向和与下电极接触。以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

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