专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20050191855A1 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US20050191855A1
公开(公告)日：2005-09-01
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

72. 发明申请

US20050133059A1 Method for cleaning a plasma enhanced CVD chamber 有权
标题翻译：清洁等离子体增强CVD室的方法
公开(公告)号：US20050133059A1
公开(公告)日：2005-06-23
申请号：US10738740
申请日：2003-12-17
申请人： Sheng-Wen Chen , Shiu-Ko Jangjian , Hung-Jui Chang , Ying-Lang Wang
发明人： Sheng-Wen Chen , Shiu-Ko Jangjian , Hung-Jui Chang , Ying-Lang Wang
IPC分类号： B08B6/00 , B08B7/00 , C23C16/44 , H01L21/00 , H01L21/30 , H01L21/3065
CPC分类号： C23C16/4405 , B08B7/00 , H01L21/67069 , Y10S134/902 , Y10S438/905
摘要： A method for plasma cleaning a CVD reactor chamber including providing a plasma enhanced CVD reactor chamber comprising residual deposited material; performing a first plasma process comprising an oxygen containing plasma; performing a second plasma process comprising an argon containing plasma; and, performing a third plasma process comprising a fluorine containing plasma.
摘要翻译：一种用于等离子体清洗CVD反应器室的方法，包括提供包含残余沉积材料的等离子体增强CVD反应器室; 执行包含含氧等离子体的第一等离子体工艺; 执行包括含氩等离子体的第二等离子体工艺; 以及执行包括含氟等离子体的第三等离子体工艺。

73. 发明授权

US06903019B2 CMP process leaving no residual oxide layer or slurry particles 失效
标题翻译： CMP工艺不留下残留的氧化物层或浆料颗粒
公开(公告)号：US06903019B2
公开(公告)日：2005-06-07
申请号：US10706495
申请日：2003-11-12
申请人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
发明人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
IPC分类号： C09G1/02 , H01L21/321 , H01L21/768 , H01L21/461
CPC分类号： C09G1/02 , H01L21/3212 , H01L21/7684
摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.
摘要翻译：当前执行的CMP中看到的两个问题是浆料颗粒保留在表面上并形成最后一层氧化物的倾向。这些问题已经通过向浆料中加入一定量的TMAH或TBAH来解决。这具有使表面被抛光的疏水性的效果。在该状态下，在CMP结束时，残留的氧化层不会残留在表面上。许多浆料磨料颗粒也不会保持粘附到新鲜抛光的表面。那些可以通过简单的冲洗或抛光容易地去除。作为替代方案，CMP工艺可以在三个阶段进行 - 第一个惯例CMP，然后在TMAH或TBAH的溶液中抛光，最后进行温和的冲洗或抛光。

74. 发明申请

US20050056544A1 Dual contact ring and method for metal ECP process 有权
标题翻译：双接触环和金属ECP工艺方法
公开(公告)号：US20050056544A1
公开(公告)日：2005-03-17
申请号：US10664347
申请日：2003-09-16
申请人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Ke-Wei Chen , Ying-Lang Wang
IPC分类号： C25D5/02 , C25D5/48 , B23H7/26
CPC分类号： C25D5/48 , C25D5/028 , Y10S204/07
摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
摘要翻译：用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。外部电压环连接到正电压源，内部电压环连接到负电压源。内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

75. 发明授权

US06291872B1 Three-dimensional type inductor for mixed mode radio frequency device 有权
标题翻译：用于混合模式射频设备的三维型电感器
公开(公告)号：US06291872B1
公开(公告)日：2001-09-18
申请号：US09433255
申请日：1999-11-04
申请人： Ying-Lang Wang , Hway-Chi Lin , Jun Wu , Jowei Dun
发明人： Ying-Lang Wang , Hway-Chi Lin , Jun Wu , Jowei Dun
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01F17/0013 , H01L27/08
摘要： Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.
摘要翻译：公开了集成电路电感器的垂直型结构。这些垂直型电感器包括在本发明中形成三个不同实施例的单环型，并联环型和螺旋型。在第一实施例中，采用单环型的三维型结构作为集成电路电感器。该电感器结构形成在基板上，并且该结构的轴线垂直于基板。在根据本发明的另一实施例中，提供了一种用于射频（RF）集成电路电感器的并联环路结构。根据本发明的螺杆型结构是第三实施例。它具有平行于衬底表面并进入半导体器件的轴线。

76. 发明授权

US06268274B1 Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry 有权
标题翻译：用于在硅晶片集成电路中形成金属间间隙填充绝缘层的低温工艺
公开(公告)号：US06268274B1
公开(公告)日：2001-07-31
申请号：US09418032
申请日：1999-10-14
申请人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
发明人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
IPC分类号： H01L2100
CPC分类号： H01L21/76801 , H01L21/31612 , H01L21/76837 , Y10S438/937
摘要： This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.
摘要翻译：本发明提供了一种在冷却期间分离的原位低温两步沉积HDP-CVD工艺，用于形成用于集成电路结构的金属间介电钝化层。所述方法减轻金属线缺陷，例如在蚀刻/沉积工艺期间产生的过多热引起的变形或翘曲。

77. 发明授权

US10643853B2 Wafer thinning apparatus having feedback control and method of using 有权
公开(公告)号：US10643853B2
公开(公告)日：2020-05-05
申请号：US13371046
申请日：2012-02-10
申请人： Yuan-Hsuan Chen , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
发明人： Yuan-Hsuan Chen , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
IPC分类号： H01L21/306 , H01L21/304 , B24B49/05 , B24B49/04 , B24B37/005 , B24B49/00 , B24B37/04 , H01L21/66
CPC分类号： H01L21/30625 , B24B37/005 , B24B37/04 , B24B49/00 , B24B49/04 , B24B49/05 , H01L21/304 , H01L22/12 , H01L22/20
摘要： A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.

78. 发明授权

US09721984B2 Image sensor manufacturing methods 有权
公开(公告)号：US09721984B2
公开(公告)日：2017-08-01
申请号：US13445766
申请日：2012-04-12
申请人： Mu-Han Cheng , Kuo-Hsiu Wei , Kei-Wei Chen , Ying-Lang Wang
发明人： Mu-Han Cheng , Kuo-Hsiu Wei , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L27/146
CPC分类号： H01L27/14623 , H01L27/1464 , H01L27/14687
摘要： Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.

79. 发明授权

US09570311B2 Modular grinding apparatuses and methods for wafer thinning 有权
标题翻译：用于晶片薄化的模块化研磨装置和方法
公开(公告)号：US09570311B2
公开(公告)日：2017-02-14
申请号：US13370946
申请日：2012-02-10
申请人： Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
发明人： Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
IPC分类号： H01L21/304 , B24B37/04 , B24B37/00
CPC分类号： H01L21/304 , B24B37/00 , B24B37/042
摘要： Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.
摘要翻译：公开了使多个半导体晶片变薄的方法及其实施方法。一组研磨模块内的研磨模块接收并研磨半导体晶片。抛光模块从研磨模块接收半导体晶片并抛光晶片。抛光模块被配置为在比研磨模块构造成磨碎相应晶片的时间少的时间内抛光半导体晶片。

80. 发明授权

US09379275B2 Apparatus and method for reducing dark current in image sensors 有权
标题翻译：降低图像传感器暗电流的装置和方法
公开(公告)号：US09379275B2
公开(公告)日：2016-06-28
申请号：US13436364
申请日：2012-03-30
申请人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
发明人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
IPC分类号： H01L31/18 , H01L31/103 , H01L27/146
CPC分类号： H01L31/1804 , H01L27/1462 , H01L27/1464 , H01L31/103 , Y02E10/547 , Y02P70/521
摘要： A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
摘要翻译：一种用于减小图像传感器中的暗电流的方法包括提供背面照射的图像传感器晶片，在背面照射的图像传感器晶片的背面上沉积第一钝化层，在第一钝化层上沉积等离子体增强的钝化层并沉积第二钝化层层上的等离子体增强钝化层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式