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71. 发明授权

US07564319B2 Vertical LC tank device 失效
标题翻译：垂直液相色谱槽装置
公开(公告)号：US07564319B2
公开(公告)日：2009-07-21
申请号：US11859850
申请日：2007-09-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H03B5/08 , H01F5/00 , H01L29/00
CPC分类号： H03L7/099 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/0617 , H01L27/0641 , H01L27/08 , H01L27/0811 , H01L28/10 , H01L2924/0002 , H03J3/20 , H01L2924/00
摘要： An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.
摘要翻译：一种LC粘结结构。该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

72. 发明申请

US20090026912A1 INTENSITY MODULATED ELECTRON BEAM AND APPLICATION TO ELECTRON BEAM BLANKER 审中-公开
标题翻译：强度调制电子束和应用于电子束保护膜
公开(公告)号：US20090026912A1
公开(公告)日：2009-01-29
申请号：US11829034
申请日：2007-07-26
申请人： Vincenzo Lordi , Kirkwood Rough , Xuefeng Liu , Shem-Tov Levi
发明人： Vincenzo Lordi , Kirkwood Rough , Xuefeng Liu , Shem-Tov Levi
IPC分类号： H01J37/302 , H01J29/51 , H01J37/30
CPC分类号： H01J37/063 , B82Y10/00 , B82Y40/00 , H01J37/045 , H01J37/073 , H01J37/075 , H01J37/3174 , H01J2237/0432
摘要： Method and apparatus for achieving an intensity modulated electron blanker are disclosed. An apparatus includes a cathode exposed to an activation source to generate an electron beam. Cathode control circuitry adjusts a cathode control amplifier to regulate cathode voltage and the potential of the electron beam. In some approaches the electron beam potential is used to control the blanking frequency, switching speeds, and duty cycle. In another approach electron generating beams directed on to the cathode are modulated to control the electron beam.
摘要翻译：公开了用于实现强度调制的电子消除器的方法和装置。一种装置包括暴露于激活源的阴极以产生电子束。阴极控制电路调节阴极控制放大器以调节阴极电压和电子束的电位。在一些方法中，电子束电位用于控制消隐频率，开关速度和占空比。在另一种方法中，调节指向阴极的电子产生光束以控制电子束。

73. 发明申请

US20080142861A1 SYMMETRIC CAPACITOR STRUCTURE 审中-公开
标题翻译：对称电容结构
公开(公告)号：US20080142861A1
公开(公告)日：2008-06-19
申请号：US12029748
申请日：2008-02-12
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/94
CPC分类号： H01L27/0805
摘要： A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：一种包括形成在衬底内的第一掺杂区，第二掺杂区，第三掺杂区和第一浅沟槽隔离结构的结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

74. 发明申请

US20070105354A1 BURIED SUBCOLLECTOR FOR HIGH FREQUENCY PASSIVE DEVICES 失效
标题翻译：用于高频无源器件的BURIED SUBCOLLECTOR
公开(公告)号：US20070105354A1
公开(公告)日：2007-05-10
申请号：US11164108
申请日：2005-11-10
申请人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
IPC分类号： H01L21/425
CPC分类号： H01L21/8249 , H01L29/0821 , H01L29/66272
摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.
摘要翻译：一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比）。本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

75. 发明申请

US20060060887A1 SiGe HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) AND METHOD OF FABRICATION 失效
标题翻译： SiGe异质双极晶体管（HBT）和制造方法
公开(公告)号：US20060060887A1
公开(公告)日：2006-03-23
申请号：US10711482
申请日：2004-09-21
申请人： Peter Geiss , Alvin Joseph , Rajendran Krishnasamy , Xuefeng Liu
发明人： Peter Geiss , Alvin Joseph , Rajendran Krishnasamy , Xuefeng Liu
IPC分类号： H01L31/109
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.
摘要翻译：在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。在基板上形成基极区域，在基极区域上形成发射极区域。集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。

76. 发明申请

US20140239498A1 SILICIDED TRENCH CONTACT TO BURIED CONDUCTIVE LAYER 审中-公开
标题翻译：硅胶触点接触到导电层
公开(公告)号：US20140239498A1
公开(公告)日：2014-08-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/48 , H01L23/482
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

77. 发明申请

US20140183753A1 FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES 有权
标题翻译：制造POLYSILICON MOS器件和被动ESD器件
公开(公告)号：US20140183753A1
公开(公告)日：2014-07-03
申请号：US13733243
申请日：2013-01-03
申请人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Junjun Li , Xuefeng Liu , Anthony K. Stamper
发明人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Junjun Li , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L27/04 , H01L21/36
CPC分类号： B81C1/00301 , B81B7/007 , B81B2207/094 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , H01L21/84 , H01L27/1203
摘要： A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.
摘要翻译：描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。介电层沉积在导电层顶上，并且通孔形成在电介质层中。另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。然后通过排气孔去除上部和下部硅牺牲膜。

78. 发明授权

US08399927B2 Semiconductor structure including a high performance fet and a high voltage fet on an SOI substrate 有权
标题翻译：包括在SOI衬底上的高性能fet和高电压fet的半导体结构
公开(公告)号：US08399927B2
公开(公告)日：2013-03-19
申请号：US13367646
申请日：2012-02-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/148
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

79. 发明申请

US20120326798A1 ON-CHIP TRANSMISSION LINE STRUCTURES WITH BALANCED PHASE DELAY 有权
标题翻译：具有平衡相位延迟的片上传输线结构
公开(公告)号：US20120326798A1
公开(公告)日：2012-12-27
申请号：US13168512
申请日：2011-06-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01P3/08 , H05K13/00 , H05K9/00 , G06F17/50
CPC分类号： H01L23/5222 , H01L23/5225 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01P1/184 , Y10T29/49117 , H01L2924/00
摘要： A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.
摘要翻译：一种传输线路结构，相关设计结构及其相关方法。公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为基本上与第二部分相同。

80. 发明申请

US20120126319A1 LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE 有权
标题翻译：具有排水区域的侧向扩散场效应晶体管与电极电极对齐
公开(公告)号：US20120126319A1
公开(公告)日：2012-05-24
申请号：US13364663
申请日：2012-02-02
申请人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1045 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
摘要翻译：形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。因此，漏极区域与栅电极的边缘自对准。一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。在形成漏极区域之后，一次性结构被去除。漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

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