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71. 发明授权

US07830698B2 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US07830698B2
公开(公告)日：2010-11-09
申请号：US12153872
申请日：2008-05-27
申请人： Xiying Chen , Bing K. Yen , Dat Nguyen , Huiwen Xu , George Samachisa , Tanmay Kumar , Er-Xuan Ping
发明人： Xiying Chen , Bing K. Yen , Dat Nguyen , Huiwen Xu , George Samachisa , Tanmay Kumar , Er-Xuan Ping
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/00 , G11C13/0069 , G11C13/025 , G11C2013/009 , G11C2213/35 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/149 , H01L45/1616 , H01L45/1675
摘要： A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.
摘要翻译：非易失性存储单元包括与存储元件串联定位的转向元件。存储元件包括碳材料，并且存储单元包括具有多个存储器级别的可重写单元。

72. 发明申请

US20100148324A1 Dual Insulating Layer Diode With Asymmetric Interface State And Method Of Fabrication 有权
标题翻译：双绝缘层二极管与不对称接口状态及制作方法
公开(公告)号：US20100148324A1
公开(公告)日：2010-06-17
申请号：US12336410
申请日：2008-12-16
申请人： Xiying Chen , Deepak Chandra Sekar , Mark Clark , Dat Nguyen , Tanmay Kumar
发明人： Xiying Chen , Deepak Chandra Sekar , Mark Clark , Dat Nguyen , Tanmay Kumar
IPC分类号： H01L29/868
CPC分类号： H01L27/2481 , H01L27/2418 , H01L45/00
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。二极管是具有第一金属层，第一绝缘层，第二绝缘层和第二金属层的金属绝缘体二极管。在至少两个层的交叉处提供至少一个非对称界面状态，以增加二极管的导通电流与其反向偏置漏电流的比率。在各种示例中，非对称界面状态由改变二极管的一个或多个部分处的势垒高度和/或电场的正或负片电荷形成。诸如无源元件存储单元的两端器件可以将二极管用作与状态改变元件串联的转向元件。可以在上下导体的交点处使用支柱结构形成装置。

73. 发明授权

US07706169B2 Large capacity one-time programmable memory cell using metal oxides 失效
标题翻译：大容量一次性可编程存储单元，使用金属氧化物
公开(公告)号：US07706169B2
公开(公告)日：2010-04-27
申请号：US12005277
申请日：2007-12-27
申请人： Tanmay Kumar
发明人： Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0078 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/72
摘要： A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.
摘要翻译：非易失性存储器件的编程方法包括：（i）提供包括与至少一种金属氧化物串联的二极管的非易失性存储单元，（ii）施加第一正向偏压以从第一状态改变金属氧化物的电阻率状态到第二个状态（iii）施加第二正向偏压以将金属氧化物的电阻率状态从第二状态改变到第三状态; 和（iv）施加第三正向偏压以将金属氧化物的电阻率状态从第三状态改变到第四状态。第四电阻率状态高于第三电阻率状态，第三电阻率状态低于第二电阻率状态，第二电阻率状态低于第一电阻率状态。

74. 发明申请

US20100078759A1 MIIM DIODES HAVING STACKED STRUCTURE 有权
标题翻译：具有堆叠结构的MIIM二极管
公开(公告)号：US20100078759A1
公开(公告)日：2010-04-01
申请号：US12240785
申请日：2008-09-29
申请人： Deepak C. Sekar , Tanmay Kumar , Peter Rabkin , Er-Xuan Ping , Xiying Chen
发明人： Deepak C. Sekar , Tanmay Kumar , Peter Rabkin , Er-Xuan Ping , Xiying Chen
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/144 , H01L45/149
摘要： A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises first and second electrode and first and second insulators arraigned as follows. An insulating region has a trench formed therein. The trench has a bottom and side walls. The first electrode, which comprises a first metal, is on the side walls and over the bottom of the trench. A first insulator has a first interface with the first electrode. At least a portion of the first insulator is within the trench. A second insulator has a second interface with the first insulator. At least a portion of the second insulator is within the trench. The second electrode, which comprises a second metal, is in contact with the second insulator. The second electrode at least partially fills the trench.
摘要翻译：公开了一种金属绝缘体二极管。在一个方面，金属绝缘体二极管包括第一和第二电极以及第一和第二绝缘体，如下所述。绝缘区域中形成有沟槽。沟槽有一个底部和侧壁。第一电极包括第一金属，位于沟槽的侧壁和底部的上方。第一绝缘体具有与第一电极的第一界面。第一绝缘体的至少一部分在沟槽内。第二绝缘体具有与第一绝缘体的第二接口。第二绝缘体的至少一部分在沟槽内。包括第二金属的第二电极与第二绝缘体接触。第二电极至少部分地填充沟槽。

75. 发明申请

US20090258462A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20090258462A1
公开(公告)日：2009-10-15
申请号：US12489214
申请日：2009-06-22
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

76. 发明申请

US20090257266A1 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US20090257266A1
公开(公告)日：2009-10-15
申请号：US12153873
申请日：2008-05-27
申请人： Xiying Chen , Tanmay Kumar
发明人： Xiying Chen , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , B82Y10/00 , G11C11/56 , G11C13/0069 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/19 , G11C2213/35 , G11C2213/72
摘要： A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located in series with a storage element, and the storage element includes a carbon material.
摘要翻译：非易失性存储单元的编程方法包括施加至少一个具有至少1ms的持续时间的初始化脉冲，然后施加持续时间小于1ms的多个编程脉冲。电池包括与存储元件串联设置的转向元件，并且存储元件包括碳材料。

77. 发明申请

US20080013364A1 Method of making non-volatile memory cell with embedded antifuse 有权
标题翻译：制造具有嵌入式反熔丝的非易失性存储单元的方法
公开(公告)号：US20080013364A1
公开(公告)日：2008-01-17
申请号：US11819595
申请日：2007-06-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： G11C11/00 , H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0676
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成至少一个非易失性存储单元，该非易失性存储单元包括第一二极管部分，第二二极管部分和将第一二极管部分与第二二极管部分分离的反熔丝，以及形成第二电极在所述至少一个非易失性存储单元上。

78. 发明申请

US20070228414A1 Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride 有权
标题翻译：异质结装置包括半导体和电阻率切换氧化物或氮化物
公开(公告)号：US20070228414A1
公开(公告)日：2007-10-04
申请号：US11395419
申请日：2006-03-31
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： H01L29/732
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
摘要翻译：在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。该p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成; 例如二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

79. 发明申请

US20070070690A1 Method for using a multi-use memory cell and memory array 有权
标题翻译：使用多用途存储单元和存储器阵列的方法
公开(公告)号：US20070070690A1
公开(公告)日：2007-03-29
申请号：US11496984
申请日：2006-07-31
申请人： Roy Scheuerlein , Tanmay Kumar
发明人： Roy Scheuerlein , Tanmay Kumar
IPC分类号： G11C11/14
CPC分类号： G11C11/5692 , G11C11/005 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C17/14 , G11C2211/5641 , G11C2211/5646 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/148
摘要： A method for using a multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.
摘要翻译：公开了一种使用多用存储单元和存储器阵列的方法。在一个优选实施例中，存储器单元可操作为一次性可编程存储器单元或可重写存储单元。存储单元包括存储元件，其包括可配置为至少三种电阻率状态之一的半导体材料，其中当存储器单元作为一次可编程存储单元操作时，第一电阻率状态用于表示存储单元的数据状态但是当存储器单元作为可重写存储单元时不起作用。还公开了具有这种存储单元的存储器阵列。在另一个优选实施例中，提供了一种包括可切换电阻材料的存储单元，其中存储单元可在第一模式中操作，其中存储单元用正向偏置和第二模式编程，其中存储单元用反向偏差。

80. 发明授权

US08971088B1 Multi-level cell operation using zinc oxide switching material in non-volatile memory device 有权
标题翻译：在非易失性存储器件中使用氧化锌切换材料的多级电池操作
公开(公告)号：US08971088B1
公开(公告)日：2015-03-03
申请号：US13426869
申请日：2012-03-22
申请人： Sung Hyun Jo , Tanmay Kumar
发明人： Sung Hyun Jo , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/5628 , G11C11/1675 , G11C11/2275 , G11C11/56 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2211/562 , G11C2211/5648 , G11C2213/15
摘要： A method for programming a non-volatile memory device includes providing an as-fabricated state-change device having an aluminum doped zinc oxide material first electrode, a p++ polysilicon material second electrode, and a zinc oxide (ZnO) material state-change material there between. A first amplitude bias voltage is applied to the first electrode of the as-fabricated state-change device causing the ZnO material to change form an as-fabricated state to a first state. A second amplitude bias voltage having an opposite polarity having an amplitude similar to the first amplitude is applied to cause the ZnO to change from the first state to a second state substantially similar as the as-fabricated state. A third amplitude bias voltage having a same polarity to the first bias voltage and having an amplitude dissimilar to the first bias voltage is applied to cause the ZnO to change from the second state to a third state.
摘要翻译：用于编程非易失性存储器件的方法包括提供一种具有铝掺杂氧化锌材料第一电极，p ++多晶硅材料第二电极和氧化锌（ZnO）材料状态变化材料的制造状态改变器件之间。第一幅度偏置电压被施加到制造状态改变器件的第一电极，使得ZnO材料从制造状态改变到第一状态。施加具有与第一幅度相似的振幅相反极性的第二幅度偏置电压，以使ZnO从第一状态转变为与制造状态基本相似的第二状态。施加与第一偏置电压具有相同极性且具有与第一偏置电压不同的幅度的第三幅度偏置电压，以使ZnO从第二状态变为第三状态。

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