专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20120171826A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120171826A1
公开(公告)日：2012-07-05
申请号：US13243147
申请日：2011-09-23
申请人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
发明人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.
摘要翻译：制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔，第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

72. 发明授权

US08183136B2 Method of forming insulating layer and method of manufacturing transistor using the same 有权
标题翻译：形成绝缘层的方法和使用其制造晶体管的方法
公开(公告)号：US08183136B2
公开(公告)日：2012-05-22
申请号：US12950592
申请日：2010-11-19
申请人： Seong-Hoon Jeong , Dong-Chan Kim , Yu-Gyun Shin , Soo-Jin Hong , Deok-Hyung Lee
发明人： Seong-Hoon Jeong , Dong-Chan Kim , Yu-Gyun Shin , Soo-Jin Hong , Deok-Hyung Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/3144 , H01L21/0214 , H01L21/02332 , H01L21/0234 , H01L21/28238 , H01L29/51
摘要： Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.
摘要翻译：提供一种形成绝缘层的方法和使用该方法制造晶体管的方法。形成绝缘层的方法包括在含硅（Si）的衬底上形成包括氧化硅（SiO 2）的预备绝缘层。含有氨（NH 3）气体的反应性气体被供给到初级绝缘层。使用等离子体从氨气产生氮自由基（N *）和氢自由基（H *）。氢原子与初级绝缘层的氧结合，氮自由基与氧化硅结合，从而可以形成包含氢氧化物（OH）和氧氮化硅（SiON）的绝缘层。

73. 发明申请

US20110237037A1 Methods of Forming Recessed Channel Array Transistors and Methods of Manufacturing Semiconductor Devices 有权
标题翻译：形成嵌入式通道阵列晶体管的方法和制造半导体器件的方法
公开(公告)号：US20110237037A1
公开(公告)日：2011-09-29
申请号：US13151494
申请日：2011-06-02
申请人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要翻译：在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。可以在栅极氧化物层上形成栅电极以填充凹部。源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。因此，氧化物层可以具有均匀的厚度分布和致密结构。

74. 发明申请

US20100035425A1 Integrated Circuit Devices Having Partially Nitridated Sidewalls and Devices Formed Thereby 有权
标题翻译：具有部分氮化侧壁和由此形成的器件的集成电路器件
公开(公告)号：US20100035425A1
公开(公告)日：2010-02-11
申请号：US12536865
申请日：2009-08-06
申请人： Jeong Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
发明人： Jeong Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
IPC分类号： H01L21/28 , H01L21/283
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

75. 发明申请

US20100025749A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100025749A1
公开(公告)日：2010-02-04
申请号：US12534422
申请日：2009-08-03
申请人： Jong-Ryeol Yoo , Tai-Su Park , Jong-Hoon Kang , Dong-Chan Kim , Jeong-Do Ryu , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin
发明人： Jong-Ryeol Yoo , Tai-Su Park , Jong-Hoon Kang , Dong-Chan Kim , Jeong-Do Ryu , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin
IPC分类号： H01L27/10 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/823828 , H01L27/10873 , H01L27/10894
摘要： A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer
摘要翻译：半导体器件可以包括隔离层，栅电极，绝缘中间层，杂质区，封盖层和插塞。隔离层可以形成在衬底中。栅电极可以形成在衬底上。绝缘中间层可以形成在栅电极上。绝缘中间层可以在栅电极之间具有接触孔。杂质区域可能在通过接触孔暴露的衬底中。覆盖层可以在杂质区上。插头可能在封盖层上。因此，杂质可能不会从杂质区域中流失。结果，由于在电极层中可能不产生耗尽，所以器件可能具有改善的电特性和可靠性

76. 发明授权

US07494859B2 Semiconductor device having metal gate patterns and related method of manufacture 有权
标题翻译：具有金属栅极图案和相关制造方法的半导体器件
公开(公告)号：US07494859B2
公开(公告)日：2009-02-24
申请号：US11400243
申请日：2006-04-10
申请人： Hag-Ju Cho , Taek-Soo Jeon , Hye-Lan Lee , Sang-Bom Kang , Yu-Gyun Shin
发明人： Hag-Ju Cho , Taek-Soo Jeon , Hye-Lan Lee , Sang-Bom Kang , Yu-Gyun Shin
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4958 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.
摘要翻译：一种半导体器件，包括具有第一杂质区和第二杂质区的半导体衬底，形成在第一杂质区上的第一栅极图案和形成在第二杂质区上的第二栅极图案。第一栅极图案包括第一栅极绝缘层图案，具有第一厚度的金属层图案和第一多晶硅层图案。第二栅极图案包括第二栅极绝缘层图案，具有小于第一厚度的第二厚度的金属硅化物层图案和第二多晶硅层图案。金属硅化物层图案由与形成金属层图案的材料基本相同的材料形成。还公开了一种半导体器件的制造方法。

77. 发明申请

US20070215959A1 Semiconductor structures including accumulations of silicon boronide and related methods 审中-公开
标题翻译：半导体结构包括硅化硼的积累和相关方法
公开(公告)号：US20070215959A1
公开(公告)日：2007-09-20
申请号：US11713877
申请日：2007-03-05
申请人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
发明人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
IPC分类号： H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061
摘要： A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.
摘要翻译：半导体器件可以包括半导体衬底，半导体衬底的表面上的第一和第二源极/漏极区域以及在第一和第二源极/漏极区域之间具有沟道区域的半导体衬底的表面上的沟道区域。绝缘层图案可以在沟道区上，第一导电层图案可以在绝缘层上，并且第二导电层图案可以在第一导电层图案上。绝缘层图案可以在第一导电层图案和沟道区之间，并且第一导电层图案可以包括硼掺杂多晶硅，表面部分具有硅化硼的积累。第一导电层图案可以在第二导电层图案和绝缘层图案之间，并且第二导电层图案可以包括钨。还讨论了相关方法。

78. 发明申请

US20070032008A1 MOS semiconductor devices having polysilicon gate electrodes and high dielectric constant gate dielectric layers and methods of manufacturing such devices 审中-公开
标题翻译：具有多晶硅栅电极和高介电常数栅介电层的MOS半导体器件及其制造方法
公开(公告)号：US20070032008A1
公开(公告)日：2007-02-08
申请号：US11494100
申请日：2006-07-27
申请人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
发明人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern, a silicon nitride layer pattern and a first polysilicon layer pattern that are sequentially stacked. The second gate pattern includes a second oxide layer pattern and a second polysilicon layer pattern. Related methods are also provided.
摘要翻译：半导体器件包括分为NMOS区和PMOS区的衬底，形成在PMOS区上的第一栅极图案，以及形成在NMOS区上的第二栅极图案。第一栅极图案包括依次层叠的第一栅极氧化物层图案，金属氧化物层图案，氮化硅层图案和第一多晶硅层图案。第二栅极图案包括第二氧化物层图案和第二多晶硅层图案。还提供了相关方法。

79. 发明申请

US20060189055A1 Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer 审中-公开
标题翻译：复合层的形成方法，通过使用复合层的形成方法制造栅极结构的方法以及使用形成复合层的方法制造电容器的方法
公开(公告)号：US20060189055A1
公开(公告)日：2006-08-24
申请号：US11356399
申请日：2006-02-16
申请人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
发明人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/0228 , H01L21/02181 , H01L21/022 , H01L21/02274 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/31645 , H01L29/40114 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods of forming a composite layer, a gate structure and a capacitor are disclosed. In the methods, a first dielectric layer is atomic layer deposited on a substrate by using an oxidation gas and a first precursor gas that includes hafnium precursors. A second dielectric layer is then atomic layer deposited on the first dielectric layer by using a nitriding gas and a second precursor gas that includes hafnium precursors.
摘要翻译：公开了形成复合层，栅极结构和电容器的方法。在该方法中，第一电介质层通过使用氧化气体和包括铪前体的第一前体气体在原子层上沉积在衬底上。然后通过使用氮化气体和包括铪前体的第二前体气体将第二电介质层原子层沉积在第一介电层上。

80. 发明申请

US20060060929A1 Semiconductor transistors having surface insulation layers and methods of fabricating such transistors 失效
公开(公告)号：US20060060929A1
公开(公告)日：2006-03-23
申请号：US11215217
申请日：2005-08-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Yin Hyun , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Yin Hyun , Guk-Hyon Yon
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate is interposed between the spacers and the substrate. An inversion layer is provided in the surface region of the substrate under the surface insulation layer. The surface insulation layer is formed of a material generating large quantities of surface states at an interface between the substrate and the surface insulation layer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式