专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08183136B2 Method of forming insulating layer and method of manufacturing transistor using the same 有权
标题翻译：形成绝缘层的方法和使用其制造晶体管的方法
公开(公告)号：US08183136B2
公开(公告)日：2012-05-22
申请号：US12950592
申请日：2010-11-19
申请人： Seong-Hoon Jeong , Dong-Chan Kim , Yu-Gyun Shin , Soo-Jin Hong , Deok-Hyung Lee
发明人： Seong-Hoon Jeong , Dong-Chan Kim , Yu-Gyun Shin , Soo-Jin Hong , Deok-Hyung Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/3144 , H01L21/0214 , H01L21/02332 , H01L21/0234 , H01L21/28238 , H01L29/51
摘要： Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.
摘要翻译：提供一种形成绝缘层的方法和使用该方法制造晶体管的方法。形成绝缘层的方法包括在含硅（Si）的衬底上形成包括氧化硅（SiO 2）的预备绝缘层。含有氨（NH 3）气体的反应性气体被供给到初级绝缘层。使用等离子体从氨气产生氮自由基（N *）和氢自由基（H *）。氢原子与初级绝缘层的氧结合，氮自由基与氧化硅结合，从而可以形成包含氢氧化物（OH）和氧氮化硅（SiON）的绝缘层。

2. 发明授权

US08319260B2 Semiconductor devices having polysilicon gate layer patterns and methods of manufacturing the same 有权
标题翻译：具有多晶硅栅极层图案的半导体器件及其制造方法
公开(公告)号：US08319260B2
公开(公告)日：2012-11-27
申请号：US12805400
申请日：2010-07-29
申请人： Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
发明人： Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/7845
摘要： In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.
摘要翻译：在半导体器件中，形成半导体器件的方法包括具有第一栅极氧化层图案的第一栅极结构，包含比硅大的原子的第一多晶硅层图案和在拉伸应力下的基板上的第一硬掩模层图案。在第一栅极结构的两侧的衬底的表面下方形成N型杂质区。具有第二栅极氧化物层图案的第二栅极结构，在压缩应力下在基底上含有小于硅的原子的第二多晶硅层图案和第二硬掩模层图案。此外，在第二栅极结构的两侧在基板的表面下方形成P型杂质区。半导体器件具有良好的器件特性。

3. 发明申请

US20110079857A1 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110079857A1
公开(公告)日：2011-04-07
申请号：US12805400
申请日：2010-07-29
申请人： Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
发明人： Deok-Hyung Lee , Soo-Jin Hong , Seong-Hoon Jeong
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/7845
摘要： In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.
摘要翻译：在半导体器件中，形成半导体器件的方法包括具有第一栅极氧化层图案的第一栅极结构，包含比硅大的原子的第一多晶硅层图案和在拉伸应力下的基板上的第一硬掩模层图案。在第一栅极结构的两侧的衬底的表面下方形成N型杂质区。具有第二栅极氧化物层图案的第二栅极结构，在压缩应力下在基底上含有小于硅的原子的第二多晶硅层图案和第二硬掩模层图案。此外，在第二栅极结构的两侧在基板的表面下方形成P型杂质区。半导体器件具有良好的器件特性。

4. 发明申请

US20080093674A1 FIN FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： FIN场效应晶体管及其制造方法
公开(公告)号：US20080093674A1
公开(公告)日：2008-04-24
申请号：US11952676
申请日：2007-12-07
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

5. 发明授权

US08481416B2 Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same 有权
标题翻译：具有接触插塞和应力缓冲垫片的半导体器件及其制造方法
公开(公告)号：US08481416B2
公开(公告)日：2013-07-09
申请号：US13205461
申请日：2011-08-08
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

6. 发明申请

US20110300704A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有应力缓冲垫片的接触片的半导体器件及其制造方法
公开(公告)号：US20110300704A1
公开(公告)日：2011-12-08
申请号：US13205461
申请日：2011-08-08
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/283
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

7. 发明申请

US20100159689A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有应力缓冲垫片的接触片的半导体器件及其制造方法
公开(公告)号：US20100159689A1
公开(公告)日：2010-06-24
申请号：US12715599
申请日：2010-03-02
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/768
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

8. 发明申请

US20060118876A1 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20060118876A1
公开(公告)日：2006-06-08
申请号：US11292261
申请日：2005-11-30
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L21/338 , H01L29/76
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

9. 发明授权

US07998851B2 Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same 有权
标题翻译：具有接触插塞和应力缓冲垫片的半导体器件及其制造方法
公开(公告)号：US07998851B2
公开(公告)日：2011-08-16
申请号：US12715599
申请日：2010-03-02
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/36
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

10. 发明申请

US20060189058A1 Fin type field effect transistors and methods of manufacturing the same 有权
标题翻译：鳍式场效应晶体管及其制造方法
公开(公告)号：US20060189058A1
公开(公告)日：2006-08-24
申请号：US11359000
申请日：2006-02-22
申请人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
发明人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/78618 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.
摘要翻译：鳍型场效应晶体管包括半导体衬底，有源鳍，第一硬掩模层图案，栅极绝缘层图案，第一导电层图案和源极/漏极区域。活性鳍片包括半导体材料，并且形成在基底上并沿远离基底的主表面的方向延伸。第一硬掩模层图案形成在有源鳍片的远离表面上的基底上。栅极绝缘层形成在有源鳍片的侧壁部分上。第一导电层图案包括金属硅化物，并且形成在基板和栅极绝缘层图案的表面上，以及在第一硬掩模图案的侧壁上。源极/漏极区域形成在第一导电层图案的相对侧上的有源鳍片中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式