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71. 发明授权

US5514499A Phase shifting mask comprising a multilayer structure and method of forming a pattern using the same 失效
标题翻译：相移掩模，其包括多层结构和使用其形成图案的方法
公开(公告)号：US5514499A
公开(公告)日：1996-05-07
申请号：US249038
申请日：1994-05-25
申请人： Takayuki Iwamatsu , Kenji Kawano , Hideya Miyazaki , Shinichi Ito , Soichi Inoue , Hiroyuki Sato , Satoshi Tanaka , Koji Hashimoto
发明人： Takayuki Iwamatsu , Kenji Kawano , Hideya Miyazaki , Shinichi Ito , Soichi Inoue , Hiroyuki Sato , Satoshi Tanaka , Koji Hashimoto
IPC分类号： G03F1/00 , G03F1/26 , G03F1/32 , G03F1/34 , G03F9/00
CPC分类号： G03F1/34 , G03F1/26 , G03F1/32
摘要： A reflection phase shifting mask used to expose a pattern by forming reflected light having a phase difference upon reflection of light, includes a substrate for reflecting exposure light, a phase shifting layer formed on a portion on the substrate, and a light transmitting medium formed on the substrate and the phase shifting layer, wherein the thickness of the phase shifting layer is set such that the phase difference between light reflected by the substrate and light reflected by the phase shifting layer becomes 180.degree..
摘要翻译：用于通过在光反射时形成具有相位差的反射光来曝光图案的反射相移掩模包括反射曝光光的基板，形成在基板上的部分上的相移层和形成在基板上的光传输介质基板和相移层，其中相移层的厚度被设定为使得由基板反射的光与由相移层反射的光之间的相位差成为180度。

72. 发明授权

US08121387B2 Mask pattern verifying method 有权
标题翻译：掩模图案验证方法
公开(公告)号：US08121387B2
公开(公告)日：2012-02-21
申请号：US12052066
申请日：2008-03-20
申请人： Mitsuyo Asano , Shinji Yamaguchi , Satoshi Tanaka , Soichi Inoue , Masamitsu Itoh , Osamu Ikenaga
发明人： Mitsuyo Asano , Shinji Yamaguchi , Satoshi Tanaka , Soichi Inoue , Masamitsu Itoh , Osamu Ikenaga
IPC分类号： G06Q10/00
CPC分类号： G06T7/001 , G03F1/86 , G06T2207/10056 , G06T2207/30148
摘要： A mask pattern verifying method include obtaining first information about a hot spot from design data of a mask pattern, obtaining second information about the mask pattern actually formed on a photo mask, and determining a measuring spot of the mask pattern actually formed on the photo mask, based on the first and second information.
摘要翻译：掩模图案验证方法包括从掩模图案的设计数据获得关于热点的第一信息，获得关于实际形成在光掩模上的掩模图案的第二信息，以及确定实际形成在光掩模上的掩模图案的测量点基于第一和第二信息。

73. 发明授权

US07934175B2 Parameter adjustment method, semiconductor device manufacturing method, and recording medium 有权
标题翻译：参数调整方法，半导体器件制造方法和记录介质
公开(公告)号：US07934175B2
公开(公告)日：2011-04-26
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.
摘要翻译：用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。

74. 发明授权

US07794897B2 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 失效
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US07794897B2
公开(公告)日：2010-09-14
申请号：US11068896
申请日：2005-03-02
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

75. 发明申请

US20090186429A1 Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device 失效
标题翻译：用于校正掩模图案的方法，用于校正掩模图案的系统，程序，用于制造光掩模的方法和用于制造半导体器件的方法
公开(公告)号：US20090186429A1
公开(公告)日：2009-07-23
申请号：US12379047
申请日：2009-02-11
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.
摘要翻译：用于校正掩模图案的计算机实现方法包括：通过使用掩模图案来预测设备图案的位移以形成设备图案和处理条件的变化; 确定光学接近校正值，使得位移落在器件图案的位移公差内; 以及使用光学接近校正值来校正掩模图案。

76. 发明授权

US07526748B2 Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium 失效
标题翻译：设计图案数据准备方法，掩模图案数据准备方法，掩模制造方法，半导体器件制造方法和程序记录介质
公开(公告)号：US07526748B2
公开(公告)日：2009-04-28
申请号：US11200176
申请日：2005-08-10
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： H01J37/3026 , G03F1/36 , G03F1/68
摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.
摘要翻译：一种设计图案数据准备方法，包括基于第一设计图案数据准备第一掩模图案数据，基于第一掩模图案数据预测在与第一掩模图案相对应的晶片上形成的晶片图案，判断是否存在有限差在预定的晶片图案和要在晶片上形成的图案之间的预定容许变化量在预定的允许变化量中，选择性地校正第一设计图案数据的一部分，当有限差不在内部时，包括对应于有限差的部分通过合成对应于包括选择性校正的部分的部分的第一掩模图案数据和通过消除与包括从第一掩模选择性校正的部分相对应的部分的第一掩模图案数据而获得的数据来准备第二设计图案数据模式数据。

77. 发明授权

US07482661B2 Pattern forming method and semiconductor device manufactured by using said pattern forming method 有权
标题翻译：图案形成方法和使用所述图案形成方法制造的半导体器件
公开(公告)号：US07482661B2
公开(公告)日：2009-01-27
申请号：US11119810
申请日：2005-05-03
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： H01L27/088
CPC分类号： G03F1/36 , Y10S438/926
摘要： A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.
摘要翻译：图案形成方法包括：确定蚀刻转换差的允许值，获得在允许值内产生蚀刻转换差的图案之间的最大距离，包括主图案或两个主图案和虚设图案的图案，准备第一设计布局或者主图案与虚拟图案之间的第二距离小于最大距离的第二设计布局，其中基于第一图案进行设计数据转换，其中，主图案之间的第一距离小于最大距离，或第二设计布局以形成第一或第二设计数据，以及通过使用第一设计数据形成主图案，或者通过使用第二设计数据形成主图案和伪图案。

78. 发明申请

US20080250381A1 PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM 有权
标题翻译：参数调整方法，半导体器件制造方法和记录介质
公开(公告)号：US20080250381A1
公开(公告)日：2008-10-09
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation.
摘要翻译：用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整作为参考制造装置的制造装置可调节的参数，使其落在预定的允许变化并将调整参数定义为参考制造装置的参考参数; 使用参考制造装置从掩模获得要在基板上形成的半导体器件的图案的第一形状，以在将参考参数设置为参考制造装置并将所获得的第一形状定义为参考完成形状; 将另一个待调节制造装置的可调参数定义为待调整制造装置的待调整参数; 当将所述规定的待调整参数设定为所述待调节制造装置并且将所获得的第二形状定义为所述第二形状时，从所述掩模获得使用所述待调节制造装置在所述基板上形成的所述图案的第二形状一个待调整的成品形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 作为待调整制造装置的参数输出具有等于或小于预定参考值的差值的待调整参数或具有等于或等于或等于或等于通过重复计算小于预定的参考值。

79. 发明授权

US07396621B2 Exposure control method and method of manufacturing a semiconductor device 失效
标题翻译：曝光控制方法及制造半导体器件的方法
公开(公告)号：US07396621B2
公开(公告)日：2008-07-08
申请号：US11819375
申请日：2007-06-27
申请人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
发明人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
IPC分类号： G03F7/16 , G03F7/20 , G03F7/38 , G03F1/14
CPC分类号： G03F1/44
摘要： A method of manufacturing a semiconductor device includes preparing a projection exposure apparatus and a photomask, the photomask having a transparent substrate and a light shield film arranged in patterns to be transferred to a resist film on a wafer. The patterns include a circuit mask pattern, and first and second mark mask patterns having dimensions which change in accordance with exposure of the resist film. The method further includes forming first and second exposure monitor marks by causing phasing differences of 180 degrees and zero degrees, respectively, of light passing through the corresponding first and second mark mask patterns; measuring the first and second exposure monitor marks; calculating first and second effective exposures based on measured dimensions of the first and second exposure monitor marks; comparing variations of the first and second effective exposures; and changing at least one of a deposit condition of a front-end film formed under the resist film or a resist film coating condition if a variation of the first effective exposure differs from a variation of the second effective exposure.
摘要翻译：制造半导体器件的方法包括制备投影曝光设备和光掩模，所述光掩模具有透明基板和以图案排列的光屏蔽膜，以转印到晶片上的抗蚀剂膜。图案包括电路掩模图案，以及具有根据抗蚀剂膜的曝光而变化的尺寸的第一和第二标记掩模图案。该方法还包括通过分别通过相应的第一和第二标记掩模图案的光180度和零度的相位差来形成第一和第二曝光监视标记; 测量第一和第二曝光监视标记; 基于第一和第二曝光监视标记的测量尺寸来计算第一和第二有效曝光; 比较第一和第二有效曝光的变化; 以及如果第一有效曝光的变化与第二有效曝光的变化不同，则改变形成在抗蚀剂膜下方的前端膜的沉积条件或抗蚀剂膜涂覆条件中的至少一个。

80. 发明申请

US20050273754A1 Pattern data correction method, pattern checking method, pattern check program, photo mask producing method, and semiconductor device manufacturing method 有权
标题翻译：图案数据校正方法，图案检查方法，图案检查程序，光掩模制造方法和半导体器件制造方法
公开(公告)号：US20050273754A1
公开(公告)日：2005-12-08
申请号：US11138407
申请日：2005-05-27
申请人： Shigeki Nojima , Satoshi Tanaka , Toshiya Kotani , Kyoko Izuha , Soichi Inoue
发明人： Shigeki Nojima , Satoshi Tanaka , Toshiya Kotani , Kyoko Izuha , Soichi Inoue
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , G21K5/10 , H01L21/027
CPC分类号： G03F1/36
摘要： A pattern data correction method is disclosed, which comprises preparing an integrated circuit pattern, setting a tolerance to the pattern that is allowable error range when the pattern is transferred on a substrate, creating a target pattern within the tolerance, and making correction for the target pattern to make a first correction pattern under a predetermined condition.
摘要翻译：公开了一种图案数据校正方法，其包括：准备集成电路图案，在图案在衬底上传送时设定容许误差范围的容许度，在公差内产生目标图案，并对目标进行校正模式以在预定条件下进行第一校正模式。

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