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71. 发明申请

US20060187611A1 Method of fabricating MEMS tunable capacitor with wide tuning range 有权
标题翻译：制造具有宽调谐范围的MEMS可调电容器的方法
公开(公告)号：US20060187611A1
公开(公告)日：2006-08-24
申请号：US11408976
申请日：2006-04-24
申请人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
发明人： Seok-Jun Won , Kang-soo Chu , Weon-Hong Kim
IPC分类号： H01G5/00 , H01G7/00
CPC分类号： H01G5/0136 , H01G5/14 , H01G5/145 , H01G5/18
摘要： A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
摘要翻译： MEMS可调谐电容器及其制造方法包括在基板上的多个固定的充电板，多个具有相同高度的固定充电板被布置成梳齿形并彼此电连接，覆盖所述多个固定充电板的电容器电介质层，与所述电容器介电层间隔开并且布置在所述多个固定的充电板上的可移动的充电板结构，其中所述可移动的充电板结构包括多个相应地布置的可移动的充电板多个固定的充电板和连接到可移动的充电板结构的致动器，其允许可移动的充电板结构在水平方向上移动。

72. 发明申请

US20060079065A1 Capacitor having reaction preventing layer and methods of forming the same 失效
标题翻译：具有防反射层的电容器及其形成方法
公开(公告)号：US20060079065A1
公开(公告)日：2006-04-13
申请号：US11130647
申请日：2005-05-17
申请人： Seok-Jun Won , Dae-Jin Kwon
发明人： Seok-Jun Won , Dae-Jin Kwon
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L21/02304 , H01L21/02145 , H01L21/02178 , H01L21/022 , H01L21/02332 , H01L21/3144 , H01L27/1085 , H01L28/56 , H01L28/60
摘要： The present invention is directed to a capacitor having a reaction preventing layer and a method forming the same. A lower electrode of silicon is formed on a substrate. An assistance layer of metal oxide or metal nitride is formed on the lower electrode. A nitridation process is performed to enable the silicon of the lower electrode, the assistance layer, and nitrogen supplied by the nitridation process to react with one another, forming a reaction preventing layer comprising metal silicon oxynitride or metal silicon nitride. A high-k dielectric film and an upper electrode are formed on the reaction preventing layer.
摘要翻译：本发明涉及一种具有反应防止层的电容器及其形成方法。在基板上形成硅的下部电极。在下部电极上形成金属氧化物或金属氮化物的辅助层。进行氮化处理，使得下部电极的硅，辅助层和由氮化处理提供的氮彼此反应，形成包含金属氮氧化硅或金属氮化硅的反应防止层。在反应防止层上形成高k电介质膜和上电极。

73. 发明申请

US20050170196A1 Substrate having catalyst layer thereon and method of cleaning reaction chamber using the same 有权
标题翻译：具有催化剂层的基板及使用其的清洁反应室的方法
公开(公告)号：US20050170196A1
公开(公告)日：2005-08-04
申请号：US11046873
申请日：2005-02-01
申请人： Seok-Jun Won , Weon-Hong Kim , Min-Woo Song
发明人： Seok-Jun Won , Weon-Hong Kim , Min-Woo Song
IPC分类号： H01L21/02 , B08B7/00 , B08B9/00 , B32B3/00 , B32B15/00 , C23C16/44 , C23F4/00
CPC分类号： H01J37/32862 , B08B7/0035 , C23C16/4405 , C23F4/00 , Y10S134/902 , Y10S438/905 , Y10T428/12528 , Y10T428/24917 , Y10T428/31678
摘要： A method of cleaning a reaction chamber using a substrate having a metal catalyst thereon is disclosed. The method includes preparing a substrate having a catalyst layer to activate a cleaning gas. The substrate is introduced into the reaction chamber. Next, a cleaning gas is introduced into the reaction chamber. Contaminations in the reaction chamber are exhausted. The substrate having a metal catalyst layer is also disclosed.
摘要翻译：公开了一种使用其上具有金属催化剂的基板清洁反应室的方法。该方法包括制备具有催化剂层以激活清洁气体的基材。将基底引入反应室。接下来，将清洁气体引入反应室。反应室内的污染已经耗尽。还公开了具有金属催化剂层的基板。

74. 发明申请

US20050118335A1 Method of forming thin ruthenium-containing layer 有权
标题翻译：形成薄钌层的方法
公开(公告)号：US20050118335A1
公开(公告)日：2005-06-02
申请号：US11014214
申请日：2004-12-16
申请人： Soon-Yeon Park , Cha-Young Yoo , Seok-Jun Won
发明人： Soon-Yeon Park , Cha-Young Yoo , Seok-Jun Won
IPC分类号： H01L21/205 , C23C16/02 , C23C16/18 , C23C16/40 , C23C16/44 , C23C16/455 , H01L21/02 , H01L21/28 , H01L21/285 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , C23C16/00
CPC分类号： C23C16/0281 , C23C16/18 , C23C16/40 , C23C16/45557 , H01L28/55 , H01L28/60
摘要： A method of forming a thin ruthenium-containing layer includes performing a CVD process using butyl ruthenoscene as a ruthenium source material. The thin ruthenium-containing layer may be formed by a one-step or two-step CVD process. The one-step CVD process is performed under a constant oxygen flow rate and a constant deposition pressure. The two-step CVD process includes forming a seed layer and forming a main layer, each of which is performed under a different process condition of a deposition temperature, an oxygen flow rate, and a deposition pressure.
摘要翻译：形成薄的含钌层的方法包括使用丁基钌金属作为钌源材料进行CVD工艺。可以通过一步或两步CVD工艺形成薄的含钌层。一步CVD工艺在恒定的氧气流速和恒定的沉积压力下进行。两步CVD工艺包括形成种子层并形成主层，每个层在沉积温度，氧气流速和沉积压力的不同工艺条件下进行。

75. 发明授权

US06844610B2 Integrated circuit devices including a resistor pattern 有权
标题翻译：集成电路器件包括一个电阻器模式
公开(公告)号：US06844610B2
公开(公告)日：2005-01-18
申请号：US10672497
申请日：2003-09-25
申请人： Seok-Jun Won , Young-Wook Park
发明人： Seok-Jun Won , Young-Wook Park
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L27/08 , H01L29/00
CPC分类号： H01L28/20 , H01L27/0802 , H01L27/10894
摘要： Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred μΩ•cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.
摘要翻译：提供了用于形成包括具有所需电阻值的电阻图案的集成电路器件的方法。在集成电路基板上形成低电阻层。在与集成电路基板相对的低电阻层上形成绝缘层。在与低电阻层相反的绝缘层上形成可能具有至少约百μΩ·cm的电阻率的高电阻层。低电阻层，绝缘层和高电阻层在集成电路基板的区域中限定电阻器图案。还提供了包括由方法提供的电阻器图案的集成电路器件，并且还提供了用于形成与电阻器图案的金属触点的方法。

76. 发明授权

US06537875B2 Semiconductor memory device for reducing damage to interlevel dielectric layer and fabrication method thereof 失效
公开(公告)号：US06537875B2
公开(公告)日：2003-03-25
申请号：US09947189
申请日：2001-09-05
申请人： Seok-Jun Won , Cha-Young Yoo
发明人： Seok-Jun Won , Cha-Young Yoo
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/76802 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L27/10855
摘要： The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.

77. 发明授权

US06218260B1 Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby 失效
标题翻译：形成具有改善的电极和电介质层特性的集成电路电容器的方法以及由此形成的电容器
公开(公告)号：US06218260B1
公开(公告)日：2001-04-17
申请号：US09036356
申请日：1998-03-06
申请人： Seung-Hwan Lee , Sang-Hyeop Lee , Young-Sun Kim , Se-Jin Shim , You-Chan Jin , Ju-Tae Moon , Jin-Seok Choi , Young-Min Kim , Kyung-Hoon Kim , Kab-Jin Nam , Young-Wook Park , Seok-Jun Won , Young-Dae Kim
发明人： Seung-Hwan Lee , Sang-Hyeop Lee , Young-Sun Kim , Se-Jin Shim , You-Chan Jin , Ju-Tae Moon , Jin-Seok Choi , Young-Min Kim , Kyung-Hoon Kim , Kab-Jin Nam , Young-Wook Park , Seok-Jun Won , Young-Dae Kim
IPC分类号： H01L2120
CPC分类号： H01L28/84 , Y10S438/964
摘要： Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.
摘要翻译：形成集成电路电容器的方法包括以下步骤：通过在半导体衬底上形成导电层图案（例如，硅层）形成电容器的下电极，然后形成第一导电类型的半球形晶粒（HSG）硅表面层导电层图案。在导电层图案的外表面上包含HSG硅表面层增加给定横向尺寸的下电极的有效表面积。 HSG硅表面层还优选地充分掺杂有第一导电型掺杂剂（例如，N型），以使电容器反向偏置时可能在下电极中形成的任何耗尽层的尺寸最小化，从而提高电容器的特性 Cmin / Cmax比。扩散阻挡层（例如，氮化硅）也形成在下电极上，然后在扩散阻挡层上形成电介质层。扩散阻挡层优选由足够厚度的材料制成，以防止介电层和下电极之间的反应，并且还防止掺杂剂从HSG硅表面层向电介质层的扩散。电介质层还优选由具有高介电强度的材料形成以增加电容。

78. 发明授权

US09553094B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09553094B2
公开(公告)日：2017-01-24
申请号：US15069920
申请日：2016-03-14
申请人： Wei-Hsiung Tseng , Ju-Youn Kim , Seok-Jun Won , Jong-Ho Lee , Hye-Lan Lee , Yong-Ho Ha
发明人： Wei-Hsiung Tseng , Ju-Youn Kim , Seok-Jun Won , Jong-Ho Lee , Hye-Lan Lee , Yong-Ho Ha
IPC分类号： H01L27/092 , H01L29/49 , H01L29/43
CPC分类号： H01L27/0924 , H01L21/02126 , H01L21/0214 , H01L21/0217 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L21/845 , H01L29/165 , H01L29/41791 , H01L29/435 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6681 , H01L29/7848
摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽; 在第一沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后进行退火; 退火后，依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数调整层和栅极导体; 并在栅极导体上形成覆盖层。

79. 发明授权

US07888773B2 Semiconductor integrated circuit device having MIM capacitor and method of fabricating the same 有权
标题翻译：具有MIM电容器的半导体集成电路器件及其制造方法
公开(公告)号：US07888773B2
公开(公告)日：2011-02-15
申请号：US11588575
申请日：2006-10-27
申请人： Seok-Jun Won , Jung-Min Park
发明人： Seok-Jun Won , Jung-Min Park
IPC分类号： H01L29/94
CPC分类号： H01L27/0629 , H01L28/60
摘要： In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.
摘要翻译：在半导体集成电路器件及其形成方法中，半导体器件包括：半导体衬底; 绝缘体，位于衬底的顶部，限定绝缘体区域; 在基板上的导电层图案，所述导电层图案从公共导电层图案化，所述导电层图案包括位于绝缘体区域中的绝缘体上的第一图案部分和位于所述绝缘体区域的有源区域中的第二图案部分衬底，其中所述第二图案部分包括所述有源区中的晶体管的栅极; 以及在所述绝缘体区域中的绝缘体上的电容器，所述电容器包括：在所述导电层图案的所述第一图案部分上的下电极，所述下电极上的电介质层图案，以及所述电介质层图案上的上电极。

80. 发明授权

US07872299B2 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07872299B2
公开(公告)日：2011-01-18
申请号：US12081160
申请日：2008-04-11
申请人： Seok-Jun Won
发明人： Seok-Jun Won
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-trap insulation layer on the semiconductor substrate and having a first region and second regions having a lower density of charge-trap sites than the first region, and a gate electrode on the charge-trap insulation layer, wherein the first region is overlapped by the gate electrode and the second regions are outside of the first region.
摘要翻译：提供了非易失性存储器件及其制造方法，其可以防止或减少器件特性的劣化和击穿电压的劣化。非易失性存储器件可以包括半导体衬底，半导体衬底上的电荷阱绝缘层，并且具有第一区域和具有比第一区域更低的电荷陷阱位置密度的第二区域，阱绝缘层，其中第一区域与栅电极重叠，第二区域在第一区域的外部。

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