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71. 发明申请

US20130168759A1 FIELD EFFECT TRANSISTOR WITH A VERTICAL CHANNEL AND FABRICATION METHOD THEREOF 有权
标题翻译：具有垂直通道的场效应晶体管及其制造方法
公开(公告)号：US20130168759A1
公开(公告)日：2013-07-04
申请号：US13821944
申请日：2011-09-09
申请人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
发明人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , B82Y10/00 , H01L21/2815 , H01L29/04 , H01L29/0653 , H01L29/0657 , H01L29/0676 , H01L29/0692 , H01L29/0847 , H01L29/413 , H01L29/42376 , H01L29/66439 , H01L29/66666 , H01L29/775
摘要： Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.
摘要翻译：本文公开了具有垂直沟道的场效应晶体管及其制造方法。场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口，在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

72. 发明申请

US20130069031A1 MULTILEVEL RESISTIVE MEMORY HAVING LARGE STORAGE CAPACITY 有权
标题翻译：具有大容量存储容量的多电阻存储器
公开(公告)号：US20130069031A1
公开(公告)日：2013-03-21
申请号：US13513155
申请日：2012-02-08
申请人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
发明人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
摘要翻译：本发明公开了一种具有大存储容量的多电平电阻存储器，属于电阻式存储器的制造技术领域。电阻性存储器包括顶电极和底电极，以及插入在顶电极和底电极之间的多个开关层和有缺陷层的组合，其中，顶电极和底电极分别与开关层（诸如Ta 2 O 5，TiO 2，HfO 2的膜）和缺陷层（诸如Ti，Au，Ag的金属膜）介于切换层之间。通过使用本发明，可以提高电阻式存储器的存储容量。

73. 发明申请

US20120289004A1 FABRICATION METHOD OF GERMANIUM-BASED N-TYPE SCHOTTKY FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：基于锗的N型肖特基效应晶体管的制造方法
公开(公告)号：US20120289004A1
公开(公告)日：2012-11-15
申请号：US13390755
申请日：2011-10-14
申请人： Ru Huang , Zhiqiang Li , Yue Guo , Xia An , Quanxin Yun , Yinglong Huang , Xing Zhang
发明人： Ru Huang , Zhiqiang Li , Yue Guo , Xia An , Quanxin Yun , Yinglong Huang , Xing Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/0895 , H01L29/41783 , H01L29/517 , H01L29/66643 , H01L29/78
摘要： The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device.
摘要翻译：本发明公开了一种Ge系N型肖特基场效应晶体管的制造方法，涉及超大规模集成电路制造工艺。本发明在衬底和金属源极/漏极之间形成薄的高K电介质层。薄层一方面可能阻止金属的电子波函数在半导体禁带中引起MIGS界面态，另一方面可能会钝化Ge界面处的悬挂键。同时，由于绝缘介电层具有非常薄的厚度，并且电子可以基本上自由地通过，所以源极和漏极的寄生电阻不会显着增加。该方法可以削弱费米能级钉扎效应，使费米能级接近Ge导带的位置，降低电子势垒，从而提高Ge基肖特基晶体管的电流开关比，提高Ge NMOS器件。

74. 发明申请

US20120264311A1 SURFACE TREATMENT METHOD FOR GERMANIUM BASED DEVICE 审中-公开
标题翻译：用于基于锗的器件的表面处理方法
公开(公告)号：US20120264311A1
公开(公告)日：2012-10-18
申请号：US13318644
申请日：2011-04-08
申请人： Xia An , Yue Guo , Runsheng Wang , Ru Huang , Xing Zhang
发明人： Xia An , Yue Guo , Runsheng Wang , Ru Huang , Xing Zhang
IPC分类号： C23G1/02 , C09K15/02 , H01L21/31 , B08B3/08
CPC分类号： C23C22/34 , C23C22/73 , H01L21/02052 , H01L21/02057 , H01L21/28255 , H01L21/28512 , H01L21/28518 , H01L21/306 , H01L23/291 , H01L23/3171 , H01L29/16 , H01L29/45 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a surface treatment method for germanium based device. Through performing surface pretreatment to the germanium based device by using an aqueous solution of ammonium fluoride as a passivant, the interface state may be reduced, the formation of natural oxidation layer at the germanium surface may be inhibited, the regeneration of natural oxidation layer and the out-diffusion of the germanium based substrate material can be effectively inhibited, and the thermal stability of the metal germanide may also be increased significantly, so that the interface quality of the germanium based device is improved easily and effectively, which are advantageous to improve the performance of the germanium based transistor.
摘要翻译：本发明提供了一种用于锗基装置的表面处理方法。通过使用氟化铵水溶液作为钝化剂，对锗系器件进行表面预处理，可以降低界面状态，抑制锗表面的天然氧化层的形成，天然氧化层的再生和可以有效地抑制基于锗的基底材料的扩散，并且还可以显着提高锗的金属锗的热稳定性，从而容易且有效地改善锗基器件的界面质量，这有利于改善锗锗基晶体管的性能。

75. 发明申请

US20120190202A1 METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING 有权
标题翻译：制造半导体纳米圆环的方法
公开(公告)号：US20120190202A1
公开(公告)日：2012-07-26
申请号：US13379752
申请日：2011-09-09
申请人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
发明人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
IPC分类号： H01L21/311 , B82Y40/00
CPC分类号： B82Y40/00
摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.
摘要翻译：本发明公开了一种制造半导体纳米圆环的方法。在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本环状纳米结构。

76. 发明申请

US20120115297A1 METHOD FOR FABRICATING A TUNNELING FIELD-EFFECT TRANSISTOR 有权
标题翻译：制造隧道场效应晶体管的方法
公开(公告)号：US20120115297A1
公开(公告)日：2012-05-10
申请号：US13133643
申请日：2010-09-25
申请人： Ru Huang , Yujie Ai , Zhihua Hao , Chunhui Fan , Shuangshuang Pu , Runsheng Wang , Quanxin Yun
发明人： Ru Huang , Yujie Ai , Zhihua Hao , Chunhui Fan , Shuangshuang Pu , Runsheng Wang , Quanxin Yun
IPC分类号： H01L21/336
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.
摘要翻译：本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差引起的影响。因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件特点

77. 发明申请

US20120061637A1 3-D STRUCTURED NONVOLATILE MEMORY ARRAY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译： 3-D结构化非易失性存储器阵列及其制造方法
公开(公告)号：US20120061637A1
公开(公告)日：2012-03-15
申请号：US13131601
申请日：2011-04-01
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , LIjie Zhang , Yu Tang
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , LIjie Zhang , Yu Tang
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L27/0688 , H01L27/101 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/1691
摘要： The present invention relates to a field of nonvolatile memory technology in ULSI circuits manufacturing technology and discloses a 3D-structured resistive-switching memory array and a method for fabricating the same. The 3D-structured resistive-switching memory array according to the invention includes a substrate and a stack structure of bottom electrodes/isolation dielectric layers, deep trenches are etched in the stack structure of the bottom electrodes/the isolation dielectric layers; a resistive-switching material layer and a top electrode layer are deposited on sidewalls of the deep trenches, wherein the top electrodes and the bottom electrodes are crossed over each other on the sidewalls of the deep trenches with the resistive-switching material being interposed at cross-over points, each of the cross-over points forms one resistive-switching memory cell, and all of the resistive-switching memory cells form the 3D-structured resistive-switching memory array, and the 3D resistive-switching memory in the array are isolated by the isolation dielectric layers. According to the invention, the storage density of a resistive-switching memory can be improved, the process can be simplified, and the cost of the process can be reduced.
摘要翻译：本发明涉及ULSI电路制造技术中的非易失性存储器技术领域，并公开了一种3D结构的电阻式开关存储器阵列及其制造方法。根据本发明的3D结构的电阻式开关存储器阵列包括底部和底部电极/隔离电介质层的堆叠结构，在底部电极/隔离电介质层的堆叠结构中蚀刻深沟槽; 电阻切换材料层和顶部电极层沉积在深沟槽的侧壁上，其中顶部电极和底部电极在深沟槽的侧壁上彼此交叉，电阻切换材料插入在交叉通过点，每个交叉点形成一个电阻式开关存储单元，并且所有的电阻式开关存储单元形成三维结构的电阻式开关存储器阵列，阵列中的3D电阻式切换存储器是通过隔离绝缘层隔离。根据本发明，能够提高电阻式切换存储器的存储密度，能够简化处理，能够降低处理成本。

78. 发明申请

US20120032239A1 METHOD FOR INTRODUCING CHANNEL STRESS AND FIELD EFFECT TRANSISTOR FABRICATED BY THE SAME 有权
标题翻译：引入通道应力和场效应晶体管的方法
公开(公告)号：US20120032239A1
公开(公告)日：2012-02-09
申请号：US13131602
申请日：2011-04-01
申请人： Ru Huang , Quanxin Yun , Xia An , Xing Zhang
发明人： Ru Huang , Quanxin Yun , Xia An , Xing Zhang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/6653 , H01L29/66636 , H01L29/7833 , H01L29/7843
摘要： The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.
摘要翻译：本发明涉及CMOS超大规模集成电路，并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。根据本发明，应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间，并且通过直接接触衬底的应变介电层在沟道中诱发应变，从而改善信道的载波移动性和设备的性能。本发明的具体效果包括：通过使用具有拉伸应变的应变电介质层，可以在沟道中诱发拉伸应变，以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变，以增加通道的空穴迁移率。根据本发明，不仅引入通道应力的有效性，而且基本上也提高了场效应晶体管的器件结构，从而增加了抑制器件的短沟道效应的能力。

79. 发明申请

US20140145139A1 TRANSPARENT FLEXIBLE RESISTIVE MEMORY AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：透明柔性电阻记忆及其制造方法
公开(公告)号：US20140145139A1
公开(公告)日：2014-05-29
申请号：US13581470
申请日：2012-02-22
申请人： Ru Huang , Yu Tang , Yimao Cai , Lijie Zhang , Gengyu Yang , Shenghu Tan , Yue Pan , Poren Tang
发明人： Ru Huang , Yu Tang , Yimao Cai , Lijie Zhang , Gengyu Yang , Shenghu Tan , Yue Pan , Poren Tang
IPC分类号： H01L45/00
CPC分类号： H01L45/149 , H01L45/1675 , H01L51/0591
摘要： The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained.
摘要翻译：本发明公开了一种透明柔性电阻式存储器及其制造方法。透明柔性电阻存储器包括透明柔性衬底，在衬底上具有MIM电容器结构的存储单元，其中存储单元的底电极和顶电极是透明和柔性的，中间电阻层是透明柔性膜的聚（对二甲苯）。聚（对二甲苯）具有优异的电阻特性。在该器件中，衬底，电极和中间电阻层均由透明柔性材料形成，从而获得可用于透明柔性电子系统中的完全透明的柔性电阻性存储器。

80. 发明授权

US08722312B2 Method for fabricating semiconductor nano circular ring 有权
标题翻译：制造半导体纳米圆环的方法
公开(公告)号：US08722312B2
公开(公告)日：2014-05-13
申请号：US13379752
申请日：2011-09-09
申请人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
发明人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
IPC分类号： G03F7/20
CPC分类号： B82Y40/00
摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.
摘要翻译：本发明公开了一种制造半导体纳米圆环的方法。在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本环状纳米结构。

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