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1. 发明申请

US20120190202A1 METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING 有权
标题翻译：制造半导体纳米圆环的方法
公开(公告)号：US20120190202A1
公开(公告)日：2012-07-26
申请号：US13379752
申请日：2011-09-09
申请人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
发明人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
IPC分类号： H01L21/311 , B82Y40/00
CPC分类号： B82Y40/00
摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.
摘要翻译：本发明公开了一种制造半导体纳米圆环的方法。在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本环状纳米结构。

2. 发明授权

US08722312B2 Method for fabricating semiconductor nano circular ring 有权
标题翻译：制造半导体纳米圆环的方法
公开(公告)号：US08722312B2
公开(公告)日：2014-05-13
申请号：US13379752
申请日：2011-09-09
申请人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
发明人： Ru Huang , Yujie Al , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xia An
IPC分类号： G03F7/20
CPC分类号： B82Y40/00
摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.
摘要翻译：本发明公开了一种制造半导体纳米圆环的方法。在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本环状纳米结构。

3. 发明授权

US08372752B1 Method for fabricating ultra-fine nanowire 有权
标题翻译：超细纳米线的制造方法
公开(公告)号：US08372752B1
公开(公告)日：2013-02-12
申请号：US13543704
申请日：2012-07-06
申请人： Ru Huang , Shuai Sun , Yujie Al , Jiewen Fan , Runsheng Wang , Xiaoyan Xu
发明人： Ru Huang , Shuai Sun , Yujie Al , Jiewen Fan , Runsheng Wang , Xiaoyan Xu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B82Y40/00 , H01L29/0676
摘要： Disclosed herein is a method for fabricating an ultra fine nanowire, which relates to a manufacturing technology of a microelectronic semiconductor transistor. This method obtains a suspended ultra fine nanowire base on a combination of a mask blocking oxidation process and a stepwise oxidation process. A diameter of the suspended ultra fine nanowire fabricated by this method is precisely controlled to 20 nm by controlling a thickness of a deposited silicon nitride film and a time and temperature of the two oxidation process. Since a speed of a dry oxidation process is slower, the size of the final nanowire may be precisely controlled. This method can be used to fabricate an ultra fine nanowire with a lower cost and a higher applicability.
摘要翻译：本文公开了一种制造超细纳米线的方法，涉及微电子半导体晶体管的制造技术。该方法通过掩模阻挡氧化工艺和逐步氧化工艺的组合获得悬浮的超细纳米线基底。通过控制沉积的氮化硅膜的厚度和两个氧化过程的时间和温度，将通过该方法制造的悬浮超细纳米线的直径精确控制为20nm。由于干燥氧化工艺的速度较慢，可以精确地控制最终纳米线的尺寸。该方法可用于制造具有较低成本和较高适用性的超细纳米线。

4. 发明申请

US20120199808A1 HIGH VOLTAGE-RESISTANT LATERAL DOUBLE-DIFFUSED TRANSISTOR BASED ON NANOWIRE DEVICE 有权
标题翻译：基于纳米器件的高耐压侧向双通道晶体管
公开(公告)号：US20120199808A1
公开(公告)日：2012-08-09
申请号：US13381633
申请日：2011-04-01
申请人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Al , Jiewen Fan
发明人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Al , Jiewen Fan
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , H01L29/0649 , H01L29/0692 , H01L29/16 , H01L29/66439 , H01L29/775
摘要： The present invention provides a high voltage-resistant lateral double-diffused transistor based on a nanowire device, which relates to the field of microelectronics semiconductor devices. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s). The invention can improve the high voltage-resistant capability of a lateral double-diffused transistor based on a silicon nanowire MOS transistor.
摘要翻译：本发明提供了一种基于纳米线器件的高耐压横向双扩散晶体管，其涉及微电子半导体器件的领域。横向双扩散MOS晶体管包括沟道区，栅极电介质，栅极区，源极区，漏极区，源极延伸区和漏极端S形漂移区，其中沟道区具有侧向圆柱形硅纳米线结构，其上均匀地覆盖一层栅极电介质，栅极区在栅极电介质上，栅极区和栅极电介质完全围绕沟道区，源极延伸区位于源区和漏极端S形漂移区域位于漏极区域和沟道区域之间，排水端S形漂移区域的平面图为单个或多个S形结构的形式，并且相对介电常数为1-4的绝缘材料填充在S形结构内。本发明可以提高基于硅纳米线MOS晶体管的横向双扩散晶体管的耐高压能力。

5. 发明授权

US08673722B2 Strained channel field effect transistor and the method for fabricating the same 有权
标题翻译：应变通道场效应晶体管及其制造方法
公开(公告)号：US08673722B2
公开(公告)日：2014-03-18
申请号：US13255443
申请日：2011-03-23
申请人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
发明人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L29/1083 , H01L29/66545 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/7849
摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.
摘要翻译：本发明公开了一种应变通道场效应晶体管及其制造方法。场效应晶体管包括衬底，源极/漏极，栅极电介质层和栅极，其特征在于，“L”形复合隔离层，其包围与源极/漏极相邻的侧面的一部分沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力。

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