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71. 发明授权

US07141860B2 LDMOS transistor 有权
标题翻译： LDMOS晶体管
公开(公告)号：US07141860B2
公开(公告)日：2006-11-28
申请号：US10875105
申请日：2004-06-23
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/95 , H01L29/47
CPC分类号： H01L29/782 , H01L27/0727 , H01L29/0619 , H01L29/0653 , H01L29/47 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.
摘要翻译： LDMOS晶体管具有插入在LDMOS晶体管的掺杂区域的中心处的肖特基二极管。典型的LDMOS晶体管在中心具有漂移区域。在这种情况下，肖特基二极管被插入该漂移区的中心，其具有在正向上提供从源极到漏极连接的肖特基二极管的作用，使得漏极电压被钳位到低于PN结的电压阈值，从而避免正向偏置PN结。一种替代方案是将肖特基二极管插入其中形成源的阱，其位于LDMOS晶体管的外围。在这种情况下，肖特基二极管的形成方式不同，但仍然在正向方向上从源极到漏极连接，以在漏极处实现所需的电压钳位。

72. 发明授权

US07071518B2 Schottky device 失效
标题翻译：肖特基装置
公开(公告)号：US07071518B2
公开(公告)日：2006-07-04
申请号：US10856602
申请日：2004-05-28
申请人： Vijay Parthasarathy , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose
发明人： Vijay Parthasarathy , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/772
CPC分类号： H01L27/0727 , H01L27/0629
摘要： A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.
摘要翻译：正交肖特基二极管或具有肖特基二极管特性和MOS晶体管的器件串联耦合以提供泄漏电流和击穿电压的显着改进，只有正向电流的降低很小。在反向偏置情况下，存在小的反向偏置电流，但由于MOS晶体管，肖特基二极管两端的电压保持较小。几乎所有的反向偏置电压都跨越MOS晶体管，直到MOS晶体管故障。然而，该晶体管击穿不是最初的破坏性，因为肖特基二极管限制了电流。随着反向偏压持续增加，肖特基二极管开始吸收更多的电压。这增加了漏电流，但是在晶体管和肖特基二极管之间的击穿电压稍微相加。

73. 发明授权

US08384184B2 Laterally diffused metal oxide semiconductor device 有权
标题翻译：横向扩散金属氧化物半导体器件
公开(公告)号：US08384184B2
公开(公告)日：2013-02-26
申请号：US12882899
申请日：2010-09-15
申请人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译：这里介绍一种半导体器件和相关的制造工艺。该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。该器件还包括第二，第三，第四和第五半导体区域。第二半导体区域位于第一半导体区域的上方，具有第二导电型。第三半导体区域位于第二半导体区域的上方，具有第一导电型。第四半导体区域位于第三半导体区域的上方，具有第二导电型。第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。

74. 发明授权

US07627428B2 Method of evaluating surface deformation 失效
标题翻译：表面变形评估方法
公开(公告)号：US07627428B2
公开(公告)日：2009-12-01
申请号：US11933862
申请日：2007-11-01
申请人： Ernian Pan , Michael Bevis , Feng Han , Hao Zhou , Ronghua Zhu
发明人： Ernian Pan , Michael Bevis , Feng Han , Hao Zhou , Ronghua Zhu
IPC分类号： G01L1/00
CPC分类号： G01N3/20
摘要： The present invention generally relates to methods for rapidly calculating the surface displacement that results from an arbitrarily shaped load on the surface of a layered substrate. Some embodiments include sparse direct calculations of surface displacement in combination with interpolation methods for estimating surface displacement at other points. Some embodiments include methods for reducing computer time required for calculating surface displacement caused by an arbitrarily shaped load on a layered surface.
摘要翻译：本发明一般涉及快速计算由分层基板的表面上的任意形状的载荷产生的表面位移的方法。一些实施例包括表面位移的稀疏直接计算以及用于估计其他点处的表面位移的插值方法。一些实施例包括用于减少计算由分层表面上的任意形状的载荷引起的表面位移所需的计算机时间的方法。

75. 发明申请

US20130009243A1 LDMOS WITH ENHANCED SAFE OPERATING AREA (SOA) AND METHOD THEREFOR 有权
标题翻译：具有增强安全操作区（SOA）的LDMOS及其方法
公开(公告)号：US20130009243A1
公开(公告)日：2013-01-10
申请号：US13614722
申请日：2012-09-13
申请人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/66659
摘要： A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
摘要翻译：横向双扩散金属氧化物半导体器件包括具有第一导电性的阱区，具有第一导电类型的第一载流子再分布区，其中第二阱区位于阱区之下，以及在第二阱区下面的高掺杂掩埋层。高掺杂掩埋层具有第一导电类型，并且其掺杂剂浓度小于阱区的掺杂浓度，并且小于第一载流子再分布区的掺杂浓度，并且掩埋层与第一阱区相连。此外，公开了可以使用外延生长的横向双重扩散金属氧化物半导体器件的形成方法。

76. 发明授权

US08907419B2 LDMOS with enhanced safe operating area (SOA) and method therefor 有权
标题翻译： LDMOS具有增强的安全操作区（SOA）及其方法
公开(公告)号：US08907419B2
公开(公告)日：2014-12-09
申请号：US13614722
申请日：2012-09-13
申请人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/66659
摘要： A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
摘要翻译：横向双扩散金属氧化物半导体器件包括具有第一导电性的阱区，具有第一导电类型的第一载流子再分布区，其中第二阱区位于阱区之下，以及在第二阱区下面的高掺杂掩埋层。高掺杂掩埋层具有第一导电类型，并且其掺杂剂浓度小于阱区的掺杂浓度，并且小于第一载流子再分布区的掺杂浓度，并且掩埋层与第一阱区相连。此外，公开了可以使用外延生长的横向双重扩散金属氧化物半导体器件的形成方法。

77. 发明授权

US08344472B2 Semiconductor device and method 有权
标题翻译：半导体器件及方法
公开(公告)号：US08344472B2
公开(公告)日：2013-01-01
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L29/66
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译：使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿电压或导通电阻。在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。

78. 发明授权

US08338872B2 Electronic device with capcitively coupled floating buried layer 有权
标题翻译：具有电容耦合浮动掩埋层的电子器件
公开(公告)号：US08338872B2
公开(公告)日：2012-12-25
申请号：US12750166
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Ronghua Zhu , Weixiao Huang , Bernhard H. Grote
发明人： Vishnu K. Khemka , Tahir A. Khan , Ronghua Zhu , Weixiao Huang , Bernhard H. Grote
IPC分类号： H01L29/66 , H01L21/00 , H01L21/84
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译：使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。该改进对于LDMOS器件特别有用。

79. 发明授权

US08330220B2 LDMOS with enhanced safe operating area (SOA) and method therefor 有权
标题翻译： LDMOS具有增强的安全操作区（SOA）及其方法
公开(公告)号：US08330220B2
公开(公告)日：2012-12-11
申请号：US12769779
申请日：2010-04-29
申请人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/735
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/66659
摘要： A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
摘要翻译：横向双扩散金属氧化物半导体器件包括具有第一导电性的阱区，具有第一导电类型的第一载流子再分布区，其中第二阱区位于阱区之下，以及在第二阱区下面的高掺杂掩埋层。高掺杂掩埋层具有第一导电类型，并且其掺杂剂浓度小于阱区的掺杂浓度，并且小于第一载流子再分布区的掺杂浓度，并且掩埋层与第一阱区相连。此外，公开了可以使用外延生长的横向双重扩散金属氧化物半导体器件的形成方法。

80. 发明申请

US20120061758A1 SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20120061758A1
公开(公告)日：2012-03-15
申请号：US12882899
申请日：2010-09-15
申请人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78 , H01L29/00 , H01L21/20
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译：这里介绍一种半导体器件和相关的制造工艺。该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。该器件还包括第二，第三，第四和第五半导体区域。第二半导体区域位于第一半导体区域的上方，具有第二导电型。第三半导体区域位于第二半导体区域的上方，具有第一导电型。第四半导体区域位于第三半导体区域的上方，具有第二导电型。第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。

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