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71. 发明授权

US06869846B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
标题翻译：形成具有双介电厚度的电子结构和如此形成的结构
公开(公告)号：US06869846B2
公开(公告)日：2005-03-22
申请号：US10411850
申请日：2003-04-10
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
摘要翻译：一种包括第一装置和第二装置的结构，其中所述第二装置的电介质厚度大于所述第一装置的电介质厚度，以及形成所述结构的方法。

72. 发明授权

US06724029B2 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US06724029B2
公开(公告)日：2004-04-20
申请号：US09683831
申请日：2002-02-21
申请人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

73. 发明授权

US06596592B2 Structures and methods of anti-fuse formation in SOI 失效
公开(公告)号：US06596592B2
公开(公告)日：2003-07-22
申请号：US10066759
申请日：2002-02-06
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21336
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

74. 发明授权

US06566191B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US06566191B2
公开(公告)日：2003-05-20
申请号：US09731148
申请日：2000-12-05
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

75. 发明授权

US06563736B2 Flash memory structure having double celled elements and method for fabricating the same 有权
公开(公告)号：US06563736B2
公开(公告)日：2003-05-13
申请号：US09860736
申请日：2001-05-18
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , William R. Tonti
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , William R. Tonti
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/0458 , H01L27/115
摘要： A flash memory array having a plurality of bitlines, at least one wordline and a plurality of flash memory flash memory elements, wherein each flash memory element includes two transistors for storing two bits, and wherein each flash memory element is positioned between a pair of adjacent bitlines. A method is also presented for fabricating the flash memory array having the plurality of flash memory elements, wherein each flash memory element is configured for storing two bits.

76. 发明授权

US06518641B2 Deep slit isolation with controlled void 失效
标题翻译：深狭缝隔离带受控空隙
公开(公告)号：US06518641B2
公开(公告)日：2003-02-11
申请号：US09861274
申请日：2001-05-18
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Johnathan E. Faltermeier , William R. Tonti
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Johnathan E. Faltermeier , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L21/76232 , H01L21/764
摘要： An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.
摘要翻译：一种用于存储器阵列的隔离区域，其中隔离区域包括至少一个具有延伸到底表面的侧壁和形成在最终沟槽区域下方的狭缝区域的沟槽区域，其中狭缝区域比上覆沟槽区域窄，并且具有提供了有意形成的空隙。

77. 发明授权

US06362056B1 Method of making alternative to dual gate oxide for MOSFETs 失效
标题翻译：制造用于MOSFET的双栅极氧化物的替代方法
公开(公告)号：US06362056B1
公开(公告)日：2002-03-26
申请号：US09511567
申请日：2000-02-23
申请人： William R. Tonti , Jack A. Mandelman
发明人： William R. Tonti , Jack A. Mandelman
IPC分类号： H01L218234
CPC分类号： H01L21/82345
摘要： A method for forming depleted conductor regions in MOSFET arrays includes the steps of preparing a substrate, forming a conductor layer on the substrate, implanting a dopant species into the conductor layer, masking portions of the doped conductor layer, and counterdoping unmasked portions of the doped conductor layer to form said depleted conductor regions on the substrate. This method provides an alternative to dual gate oxide for MOSFETS wherein low voltage regions at doped layers are used for support devices and high voltage regions at counterdoped portions are used for memory arrays such as DRAM, EDRAM, SRAM and NVRAM. This method is also applicable for all chips requiring high and low voltage integral device operation.
摘要翻译：用于在MOSFET阵列中形成耗尽导体区域的方法包括以下步骤：制备衬底，在衬底上形成导体层，将掺杂物种类注入导体层，掺杂导体层的掩模部分和掺杂的掺杂物的未掺杂部分导体层以在衬底上形成所述耗尽导体区域。该方法提供了用于MOSFET的双栅极氧化物的替代方案，其中在掺杂层处的低电压区域用于支撑器件，并且在反向掺杂部分处的高电压区域用于诸如DRAM，EDRAM，SRAM和NVRAM的存储器阵列。该方法也适用于需要高，低电压一体化器件工作的所有芯片。

78. 发明授权

US06344383B1 Structure and method for dual gate oxidation for CMOS technology 失效
标题翻译：用于CMOS技术的双栅极氧化的结构和方法
公开(公告)号：US06344383B1
公开(公告)日：2002-02-05
申请号：US09421853
申请日：1999-10-20
申请人： Wayne S. Berry , Jeffrey P. Gambino , Jack A. Mandelman , William R. Tonti
发明人： Wayne S. Berry , Jeffrey P. Gambino , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L218238
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.
摘要翻译：本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成相应较薄的中心区域。

79. 发明授权

US06274467B1 Dual work function gate conductors with self-aligned insulating cap 失效
标题翻译：具有自对准绝缘帽的双功能栅极导体
公开(公告)号：US06274467B1
公开(公告)日：2001-08-14
申请号：US09327080
申请日：1999-06-04
申请人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2122
CPC分类号： H01L21/28035 , H01L21/28052 , H01L21/32155 , H01L21/823842
摘要： A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack includes a gate insulating layer formed on the substrate and a layer of polysilicon on top of the gate insulating layer. The polysilicon layer may be doped n-type remain intrinsic. A barrier layer is formed on top of the polysilicon layer and a dopant source layer is formed on top of the barrier layer. The barrier layer contains a p-type dopant. The gate stack is enclosed by an insulating cap so that a diffusion contact can be formed borderless to the gate. Activation of the dopant source layer to dope a polysilicon layer can be delayed until a desired time.
摘要翻译：提供一种具有自对准绝缘帽的双功能栅极导体及其形成方法。在衬底中形成两个扩散区域，并且在扩散区域之间的衬底上形成栅叠层。栅极堆叠包括形成在衬底上的栅极绝缘层和位于栅极绝缘层顶部的多晶硅层。多晶硅层可以掺杂n型保持固有。在多晶硅层的顶部形成阻挡层，并且在阻挡层的顶部上形成掺杂剂源层。阻挡层含有p型掺杂剂。栅极堆叠被绝缘盖封闭，使得扩散接触可以形成与栅极无边界。激发掺杂剂源层以掺杂多晶硅层可以被延迟到期望的时间。

80. 发明授权

US06150212A Shallow trench isolation method utilizing combination of spacer and fill 失效
标题翻译：使用间隔物和填充物的组合的浅沟槽隔离方法
公开(公告)号：US06150212A
公开(公告)日：2000-11-21
申请号：US359287
申请日：1999-07-22
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/762 , H01L21/8242
CPC分类号： H01L21/76232 , H01L27/10861 , H01L27/1087
摘要： A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.
摘要翻译：一种用于在半导体衬底中形成隔离沟槽区域的方法包括：在半导体衬底中设置沟槽区域，至少在沟槽区域的侧壁上添加衬垫材料，并在其底表面处蚀刻沟槽区域，以将沟槽区域延伸到下面底面并形成缝隙区域。间隔物材料可以随后被加热，使得间隔物材料从侧壁流入缝隙区域。

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