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71. 发明授权

US07479429B2 Split game memory cell method 有权
标题翻译：分割游戏记忆单元法
公开(公告)号：US07479429B2
公开(公告)日：2009-01-20
申请号：US11669307
申请日：2007-01-31
申请人： Rajesh Rao , Ramachandran Muralidhar , Leo Mathew
发明人： Rajesh Rao , Ramachandran Muralidhar , Leo Mathew
IPC分类号： H01L21/336
CPC分类号： H01L29/7923 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42344 , H01L29/7887
摘要： A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.
摘要翻译：在衬底上形成多位分离栅极存储器件。在衬底上形成存储层。在存储层上形成第一导电层。去除导电层的一部分的厚度以留下导电层的柱和导电层的厚度减小的面积。形成邻近柱的第一侧壁间隔物以覆盖导电层厚度减小区域的第一部分和第二部分。柱子被一个选择门取代。选择性地去除厚度减小的区域以留下第一和第二部分作为控制门。

72. 发明申请

US20080303094A1 SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF FORMING 有权
标题翻译：自对准的分离栅格存储单元和形成方法
公开(公告)号：US20080303094A1
公开(公告)日：2008-12-11
申请号：US11759593
申请日：2007-06-07
申请人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
发明人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
IPC分类号： H01L29/78 , H01L21/04 , H01L29/68
CPC分类号： H01L29/792 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/42332
摘要： A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.
摘要翻译：使用半导体层形成分离栅极存储器件的方法包括图案化绝缘层以留下其柱。在半导体层上形成栅极电介质。电荷存储层形成在栅极电介质上并沿着柱的第一和第二侧。栅极材料层形成在栅极电介质和支柱上。执行蚀刻以将栅极材料的第一部分横向邻近柱的第一侧并且位于栅极电介质上方的电荷存储层的第一部分上，以用作存储器件的控制栅极，并且栅极材料的第二部分横向邻近柱的第二侧，并且位于栅极电介质上方的电荷存储层的第二部分上，用作选择栅极。

73. 发明申请

US20080303067A1 SPLIT GATE MEMORY CELL USING SIDEWALL SPACERS 有权
标题翻译：分离栅格存储单元使用边框间隔
公开(公告)号：US20080303067A1
公开(公告)日：2008-12-11
申请号：US11759518
申请日：2007-06-07
申请人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
发明人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/7881
摘要： A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.
摘要翻译：自对准分离栅极位单元包括由没有电荷存储材料的间隙分开的电荷存储材料的第一和第二区域。间隔物形成在牺牲层的侧壁上，该牺牲层在位单元堆叠的上方和相对侧上延伸，其中间隔物彼此间隔至少间隙长度。刻蚀对间隔物有选择性的位单元堆叠形成了将位单元堆叠分成第一和第二栅极的间隙，这些栅极组共同构成了分离栅极位单元堆叠。比特单元堆叠的存储部分也被蚀刻，其中蚀刻延伸间隙并将相应的层分离成第一和第二分离区域，扩展间隙没有电荷存储材料。电介质材料沉积在间隙上并被回蚀以暴露牺牲层的顶表面，此牺牲层此后被去除以暴露分裂栅极位晶胞堆叠的侧壁。

74. 发明授权

US07427549B2 Method of separating a structure in a semiconductor device 有权
标题翻译：分离半导体器件中的结构的方法
公开(公告)号：US07427549B2
公开(公告)日：2008-09-23
申请号：US11278180
申请日：2006-03-31
申请人： Leo Mathew , Ramachandran Muralidhar , Veeraraghavan Dhandapani
发明人： Leo Mathew , Ramachandran Muralidhar , Veeraraghavan Dhandapani
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L29/6653 , H01L29/66825 , H01L29/66833
摘要： Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.
摘要翻译：去除半导体器件中的一部分结构以分离结构。该结构具有两个不同高度的部分。在一个示例中，通过在与较高部分的侧壁相邻的下部形成隔离物来移除结构。然后在间隔件外部的结构上形成第二材料。移除间隔物，然后移除间隔物下面的部分以在该位置分离结构。在一个实施例中，在分离的结构中实现单独的通道区域。在其他实施例中，在分离的结构中实现单独的门结构。

75. 发明授权

US07241695B2 Semiconductor device having nano-pillars and method therefor 有权
公开(公告)号：US07241695B2
公开(公告)日：2007-07-10
申请号：US11244516
申请日：2005-10-06
申请人： Leo Mathew , Rajesh A. Rao , Ramachandran Muralidhar
发明人： Leo Mathew , Rajesh A. Rao , Ramachandran Muralidhar
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , B82Y10/00 , H01L21/28273 , H01L21/32139 , H01L28/91 , H01L29/512 , H01L29/513
摘要： A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.

76. 发明申请

US20070004146A1 Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types 有权
标题翻译：用于集成嵌入式非易失性存储装置的形成与形成多晶体管器件类型的半导体制造工艺
公开(公告)号：US20070004146A1
公开(公告)日：2007-01-04
申请号：US11172728
申请日：2005-07-01
申请人： Erwin Prinz , Ramachandran Muralidhar
发明人： Erwin Prinz , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823857 , Y10S438/962
摘要： A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.
摘要翻译：半导体制造工艺包括在覆盖衬底的第一区域的隧道氧化物上形成多晶硅纳米晶体。沉积第二电介质覆盖在第一区域和第二区域上。在不提供覆盖第一区域中的第二电介质的任何保护层的情况下，进行额外的热氧化步骤而不氧化纳米晶体。然后将栅极电极膜沉积在第二电介质上并被图案化以形成第一和第二栅电极。第二电介质可以是退火的CVD氧化物。额外的热氧化可以包括通过干式氧化形成覆盖在半导体衬底的第三区域上的第三电介质。干燥氧化在第二区域中产生第二电介质下面的界面氧化硅。然后可以暴露基板的第四区域的上表面，并在第四区域的上表面上形成第四电介质。

77. 发明申请

US20060199335A1 Electronic devices including non-volatile memory structures and processes for forming the same 审中-公开
标题翻译：包括非易失性存储器结构的电子设备及其形成工艺
公开(公告)号：US20060199335A1
公开(公告)日：2006-09-07
申请号：US11071977
申请日：2005-03-04
申请人： Rajesh Rao , Ramachandran Muralidhar
发明人： Rajesh Rao , Ramachandran Muralidhar
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/66772
摘要： An electronic device can include an NVM structure and a gate electrode outside an NVM array. In one embodiment, a first gate dielectric layer and a first gate electrode layer are formed before forming NVM cells within an NVM array. The first gate electrode layer helps to protect the first gate dielectric layer from becoming thinner or thicker during subsequent processing used to form NVM cells. In another embodiment, NVM structures and transistor structures can be formed where the NVM structures have one more spacer adjacent to the NVM structures as compared to the transistor structures.
摘要翻译：电子设备可以包括NVM结构和NVM阵列外部的栅电极。在一个实施例中，在形成NVM阵列内的NVM单元之前形成第一栅极介电层和第一栅极电极层。第一栅极电极层有助于在用于形成NVM电池的后续处理期间保护第一栅极介电层变得更薄或更厚。在另一个实施例中，可以形成NVM结构和晶体管结构，其中与晶体管结构相比，NVM结构具有与NVM结构相邻的更多间隔区。

78. 发明申请

US20060030105A1 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US20060030105A1
公开(公告)日：2006-02-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
发明人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

79. 发明申请

US20050191808A1 Method for removing nanoclusters from selected regions 失效
标题翻译：从选定区域去除纳米团簇的方法
公开(公告)号：US20050191808A1
公开(公告)日：2005-09-01
申请号：US10787510
申请日：2004-02-26
申请人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
发明人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.
摘要翻译：纳米簇被覆盖在集成电路上，然后从不需要纳米团簇的区域去除。在毛毯沉积之前在纳米团簇不需要的那些区域中形成牺牲层。然后去除纳米团簇和牺牲层。在一种形式中，牺牲层包括沉积的含氮化物或含氧化物层。或者，牺牲层包括先前用于在衬底中形成隔离区域的衬垫氧化物或衬垫氮化物层中的至少一个。然后可以将纳米簇装置和非纳群集装置集成到相同的集成电路上。牺牲层的使用保护下层，从而防止随后形成的非纳群集装置的性能下降。

80. 发明授权

US06583057B1 Method of forming a semiconductor device having a layer deposited by varying flow of reactants 失效
标题翻译：形成具有通过改变反应物流而沉积的层的半导体器件的方法
公开(公告)号：US06583057B1
公开(公告)日：2003-06-24
申请号：US09211165
申请日：1998-12-14
申请人： Prasad Alluri , Ramachandran Muralidhar
发明人： Prasad Alluri , Ramachandran Muralidhar
IPC分类号： H01L2100
CPC分类号： C23C16/45523 , C23C16/409 , H01L21/02183 , H01L21/02197 , H01L21/0228 , H01L21/31612
摘要： A method of forming a semiconductor device by placing a semiconductor substrate in a vacuum chamber and subjecting the semiconductor substrate (20) to a sub-atmospheric pressure, and depositing a layer (40) on the semiconductor substrate while maintaining the sub-atmospheric pressure. Deposition of the layer (40) is carried out by sequentially (i) flowing a first reactant into the vacuum chamber at a first flow rate, (ii) reducing flow of the first reactant into the vacuum chamber to a second flow rate, and (iii) increasing flow of the first reactant into the vacuum chamber to a third flow rate.
摘要翻译：通过将半导体衬底放置在真空室中并对半导体衬底（20）施加次大气压力，并且在保持低于大气压力的同时在半导体衬底上沉积层（40）来形成半导体器件的方法。层（40）的沉积通过顺序地（i）以第一流速将第一反应物流入真空室中，（ii）将第一反应物流入真空室中的流量降至第二流量，和 iii）增加第一反应物进入真空室的流量至第三流量。

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