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71. 发明授权

US06183938B2 Conformal organic coatings for sidewall patterning of sublithographic structures 失效
标题翻译：用于亚光刻结构侧壁图案的保形有机涂层
公开(公告)号：US06183938B2
公开(公告)日：2001-02-06
申请号：US09207551
申请日：1998-12-08
申请人： Christopher F. Lyons , Michael K. Templeton
发明人： Christopher F. Lyons , Michael K. Templeton
IPC分类号： G03F700
CPC分类号： H01L21/3088 , G03F7/00 , G03F7/0035 , G03F7/0045 , H01L21/0338
摘要： In one embodiment, the present invention relates to a method of making a sub-lithographic structure involving the steps of providing a nitrogen rich film over a portion of a substrate; depositing a photoresist over the nitrogen rich film and the substrate, wherein the photoresist and the nitrogen rich film interact and form a thin desensitized resist layer around an interface between the photoresist and the nitrogen rich film; exposing the photoresist to radiation; developing the photoresist exposing the thin desensitized resist layer; directionally etching a portion of the thin desensitized resist layer; and removing the nitrogen rich film leaving the sub-lithographic structure on the substrate.
摘要翻译：在一个实施方案中，本发明涉及一种制备亚光刻结构的方法，其涉及以下步骤：在衬底的一部分上提供富氮膜; 在富氮膜和衬底上沉积光致抗蚀剂，其中光致抗蚀剂和富氮膜相互作用并在光致抗蚀剂和富氮膜之间的界面周围形成薄的脱敏抗蚀剂层; 将光致抗蚀剂暴露于辐射; 显影曝光薄的脱敏抗蚀剂层的光致抗蚀剂; 定向蚀刻一部分薄的脱敏抗蚀剂层; 并除去留在基板上的亚光刻结构的富氮膜。

72. 发明授权

US5658440A Surface image transfer etching 失效
标题翻译：表面图像转印蚀刻
公开(公告)号：US5658440A
公开(公告)日：1997-08-19
申请号：US553966
申请日：1995-11-06
申请人： Michael K. Templeton , Subhash Gupta
发明人： Michael K. Templeton , Subhash Gupta
IPC分类号： G03F7/40 , H01J37/32 , H01L21/3213 , C23C14/34
CPC分类号： H01J37/32192 , G03F7/40 , H01J37/32678 , H01L21/32137
摘要： A process called surface image transfer etching (SITE) is used to etch patterned photoresist so as to more completely transfer a well-defined pattern formed in the top surface (10a) of a material to the bulk of the material (12). The process uses no mask, but employs only a sputter etching process where the etching rates of surfaces not normal to the ion trajectories are greatly enhanced over the etching rates of surfaces normal to the ion trajectories.
摘要翻译：使用称为表面图像转移蚀刻（SITE）的工艺来蚀刻图案化的光致抗蚀剂，以便将形成在材料的顶表面（10a）中的良好限定的图案更完全地转移到材料（12）的主体上。该方法不使用掩模，而仅使用溅射蚀刻工艺，其中不垂直于离子轨迹的表面的蚀刻速率比垂直于离子轨迹的表面的蚀刻速率大大增强。

73. 发明授权

US5308740A Electrical measurement of sidewall angle 失效
标题翻译：侧壁角度的电气测量
公开(公告)号：US5308740A
公开(公告)日：1994-05-03
申请号：US947242
申请日：1992-09-18
申请人： Michael K. Templeton , Subhash Gupta
发明人： Michael K. Templeton , Subhash Gupta
IPC分类号： G03F7/26 , G03C5/00 , B44C1/22
CPC分类号： G03F7/26
摘要： A method for measuring the sidewall angle of patterned photoresist (16), as well as wall angles of other materials, is provided. The method comprises forming two copies of the patterned photoresist feature for which the sidewall measurement is to be obtained on a conducting substrate (14). The first copy is processed via conventional techniques for linewidth measurement, which consists of a pattern transfer etch of the first copy into the underlying conductive substrate, followed by electrical measurement of the conductor linewidth to yield linewidth 1 (LW1). The second copy is processed such that there is a shape altering etch prior to the pattern transfer etch. A linewidth 2 (LW2) is obtained. The angle is then extracted from the two linewidth measurements.
摘要翻译：提供了用于测量图案化光致抗蚀剂（16）的侧壁角以及其它材料的壁角的方法。该方法包括在导电衬底（14）上形成要获得侧壁测量的图案化光致抗蚀剂特征的两个拷贝。通过用于线宽测量的常规技术来处理第一个拷贝，该技术包括将第一拷贝的图案转移蚀刻到下面的导电衬底中，随后电导体线宽的线性测量以产生线宽1（LW1）。处理第二拷贝使得在图案转移蚀刻之前存在改变蚀刻的形状。得到线宽2（LW2）。然后从两个线宽测量中提取角度。

74. 发明授权

US5128230A Quinone diazide containing photoresist composition utilizing mixed solvent of ethyl lactate, anisole and amyl acetate 失效
标题翻译：使用乳酸乙酯，苯甲醚和乙酸戊酯的混合溶剂的含喹诺酮二氮化物的光致抗蚀剂组合物
公开(公告)号：US5128230A
公开(公告)日：1992-07-07
申请号：US644752
申请日：1991-01-23
申请人： Michael K. Templeton , Anthony Zampini , Peter Trefonas, III , James C. Woodbrey , David C. Madoux , Brian K. Daniels
发明人： Michael K. Templeton , Anthony Zampini , Peter Trefonas, III , James C. Woodbrey , David C. Madoux , Brian K. Daniels
IPC分类号： G03F7/004 , G03F7/022
CPC分类号： G03F7/0226 , G03F7/0048
摘要： This invention is directed to novel photoresist processes and compositions having high resolution novalac resins, high resolution photoactive components with several diazoquinone groups per molecule, and solvents having a high solvency power, better safety, improved photospeed, higher contrast and equivalent cast film thickness from lower percent solids formulations.
摘要翻译：本发明涉及具有高分辨率诺瓦克树脂的新型光刻胶工艺和组合物，每分子具有几个重氮醌基团的高分辨率光活性组分和具有高偿付能力的溶剂，更好的安全性，更高的感光速度，更高的对比度和相当的流延膜厚度从较低固含量百分数。

75. 发明授权

US06603211B2 Method and system for providing a robust alignment mark at thin oxide layers 失效
公开(公告)号：US06603211B2
公开(公告)日：2003-08-05
申请号：US09784907
申请日：2001-02-15
申请人： Michael K. Templeton , Hao Fang , Maria C. Chan , King Wai Kelwin Ko
发明人： Michael K. Templeton , Hao Fang , Maria C. Chan , King Wai Kelwin Ko
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

76. 发明授权

US06495435B2 Method for improved control of lines adjacent to a select gate using a mask assist feature 失效
标题翻译：一种使用掩模辅助功能改进与选择门相邻的线的控制的方法
公开(公告)号：US06495435B2
公开(公告)日：2002-12-17
申请号：US09788246
申请日：2001-02-15
申请人： Michael K. Templeton , Hao Fang , Maria C. Chan
发明人： Michael K. Templeton , Hao Fang , Maria C. Chan
IPC分类号： H01L2120
CPC分类号： H01L27/11521 , H01L21/76838 , H01L27/105 , H01L27/1052 , H01L27/115
摘要： A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.
摘要翻译：公开了一种用于在半导体存储器件中提供多条线的方法和系统。该方法和系统包括提供半导体衬底，提供多条线并提供相邻特征。多条线包括与相邻特征相邻的相邻线。多条线中的每条线具有对于多根线中的每条线基本相同的线宽度。优选地，利用掩模形成多条线以打印多条线和相邻特征的物理掩模。掩模包括用于相邻行的至少第一多边形和用于相邻特征的至少第二多边形之间的掩模辅助特征。掩模辅助特征具有足够大的尺寸以影响相邻线的宽度，并且足够小以防止相应的特征被印刷在物理掩模上。该方法和系统还优选地包括去除由物理掩模的图案暴露的材料层的第二部分以形成多条线。

77. 发明授权

US06445051B1 Method and system for providing contacts with greater tolerance for misalignment in a flash memory 有权
标题翻译：用于提供触点的方法和系统，其具有对于闪存中未对准的更大容限
公开(公告)号：US06445051B1
公开(公告)日：2002-09-03
申请号：US09563797
申请日：2000-05-02
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/28273
摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.
摘要翻译：公开了一种用于在闪速存储器件中提供多个触点的方法和系统。闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。该方法和系统还包括蚀刻绝缘层以提供多个接触孔。绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤不会蚀刻穿过多个场绝缘区域。该方法和系统还包括用导体填充多个接触孔。

78. 发明授权

US06316804B1 Oxygen implant self-aligned, floating gate and isolation structure 失效
标题翻译：氧气注入自对准，浮动门和隔离结构
公开(公告)号：US06316804B1
公开(公告)日：2001-11-13
申请号：US09569721
申请日：2000-05-11
申请人： Michael K. Templeton , Kathleen R. Early
发明人： Michael K. Templeton , Kathleen R. Early
IPC分类号： H01L29788
CPC分类号： H01L27/11521
摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.
摘要翻译：一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。浮动栅极可以形成为相对于下面的有源区域具有最小宽度。

79. 发明授权

US6093967A Self-aligned silicide contacts formed from deposited silicon 失效
标题翻译：由沉积硅形成的自对准硅化物触点
公开(公告)号：US6093967A
公开(公告)日：2000-07-25
申请号：US992573
申请日：1997-12-17
申请人： Yowjuang W. Liu , Mark S. Chang , Michael K. Templeton
发明人： Yowjuang W. Liu , Mark S. Chang , Michael K. Templeton
IPC分类号： H01L21/285 , H01L23/54 , H01L21/441
CPC分类号： H01L21/28518
摘要： Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon may be amorphous silicon in which case the deposition temperature can be as low as 580.degree. C. If polysilicon is deposited, the deposition temperature has to be at least 620.degree. C.
摘要翻译：通过在衬底的有源区上沉积硅，在硅上沉积难熔金属，并加热硅和难熔金属，形成具有至少约等于栅极高度的高度的自对准硅化物触点。沉积的硅可以是非晶硅，在这种情况下，沉积温度可以低至580℃。如果沉积多晶硅，则沉积温度必须至少为620℃。

80. 发明授权

US6066530A Oxygen implant self-aligned, floating gate and isolation structure 失效
标题翻译：氧气注入自对准，浮动门和隔离结构
公开(公告)号：US6066530A
公开(公告)日：2000-05-23
申请号：US57992
申请日：1998-04-09
申请人： Michael K. Templeton , Kathleen R. Early
发明人： Michael K. Templeton , Kathleen R. Early
IPC分类号： H01L21/8247 , H01L21/336
CPC分类号： H01L27/11521
摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.
摘要翻译：一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。浮动栅极可以形成为相对于下面的有源区域具有最小宽度。

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