专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US5898597A Integrated circuit floor plan optimization system 失效
标题翻译：集成电路平面图优化系统
公开(公告)号：US5898597A
公开(公告)日：1999-04-27
申请号：US798652
申请日：1997-02-11
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions. Then, pieces of the core space are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used shift the allocated capacities of the functions as to shift excess capacity or core space from the functions with excess capacity to the functions with a shortage of capacity.
摘要翻译：公开了一种用于规划每个功能的集成电路的楼层分配的方法。为了为每个功能提供足够的核心空间并且满足诸如每个功能的空间利用要求的一些成本函数，所公开的方法将核心空间划分为基本区域的网格。然后，确定核心空间的块，并且识别包含边界的部分和功能的重叠区域。然后，使用所识别的部件将功能的分配能力转移到将过剩容量或核心空间从具有过剩容量的功能转移到容量不足的功能中。

72. 发明授权

US5867398A Advanced modular cell placement system with density driven capacity penalty system 失效
标题翻译：先进的模块化电池放置系统，具有密度驱动能力罚款系统
公开(公告)号：US5867398A
公开(公告)日：1999-02-02
申请号：US672534
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5072
摘要： A system for ascertaining the penalty associated with relocating a cell located on a surface of a semiconductor chip to an alternate location is disclosed herein. The system comprises a region capacity calculator for determining a capacity of cells which will fit in the current region, a height capacity calculator for determining the sum of heights for all cells located in each region, a basic penalty calculator which computes a basic penalty associated with relocating the cell to another location based on the capacity and heights of cells for the current region and the capacity and heights of cells in the proposed region, and a total penalty calculator for computing the total penalty associated with the basic penalty, penalties associated with multiple regions, and cell capacity for the current cell.
摘要翻译：本文公开了一种用于确定将位于半导体芯片的表面上的单元重新定位到交替位置的惩罚的系统。该系统包括用于确定适合当前区域的单元的容量的区域容量计算器，用于确定位于每个区域中的所有单元的高度之和的高度容量计算器，计算与基于当前区域的单元的容量和高度以及所提出的区域中的单元的容量和高度将单元重定位到另一位置，以及用于计算与基本罚分相关联的总惩罚的总惩罚计算器，与多个相关联的惩罚区域和当前单元的单元容量。

73. 发明授权

US5838585A Physical design automation system and method using monotonically improving linear clusterization 失效
标题翻译：物理设计自动化系统和使用单调改进线性聚类的方法
公开(公告)号：US5838585A
公开(公告)日：1998-11-17
申请号：US986753
申请日：1997-12-08
申请人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Stanislav V. Aleshin , Alexander E. Andreev , Alexander S. Podkolzin
发明人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Stanislav V. Aleshin , Alexander E. Andreev , Alexander S. Podkolzin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An initial placement of cells, and a routing including wires interconnecting the cells, is provided for a microelectronic integrated circuit. A grid is defined as including a plurality of first gridlines that extend parallel to a first axis, and a plurality of second gridlines that extend parallel to a second axis that is angularly displaced from the first axis. The cells are represented as vertices located at intersections of first and second gridlines, and the wires are represented as edges that extend along the first and second gridlines. Clusters of vertices are created such that each cluster includes vertices located on a respective first gridline. A "cover" is computed as including a minimum block of clusters that are connected to all other clusters by wires extending along the second gridlines. Clusters outside the cover are spatially reordered along the second axis away from the cover in descending order of numbers of wires extending from the clusters along the second gridlines. The placement is then updated and rerouted, and these operations are performed in the opposite direction and the two perpendicular directions. A quality factor, preferably the total wirelength of the routing, is computed and compared to a previous value. The entire operation is iteratively performed until the improvement in quality factor between consecutive iterations becomes less than a predetermined value. Due to the nature of the reordering, the quality factor improves monotonically for each iteration. The rerouting steps can be omitted, and edges defined by bounding boxes constructed around interconnect nets.
摘要翻译：微电子集成电路提供了单元的初始放置以及包括互连电池的布线的布线。网格被定义为包括平行于第一轴线延伸的多个第一网格线和平行于从第一轴线成角度地移位的第二轴线延伸的多个第二网格线。细胞被表示为位于第一和第二网格线的交点处的顶点，并且线被表示为沿着第一和第二网格线延伸的边缘。创建顶点簇，使得每个簇包括位于相应的第一网格线上的顶点。 “盖”被计算为包括通过沿着第二网格线延伸的线连接到所有其他簇的最小块簇。盖子之外的群集沿着沿着第二网格线从群集延伸的导线的数量的降序沿着沿着第二轴的空间重新排列。然后更新和重新路由放置，并且这些操作在相反方向和两个垂直方向上执行。计算质量因子，优选路由的总线长，并将其与先前值进行比较。迭代执行整个操作，直到连续迭代之间的质量因子的改善变得小于预定值。由于重新排序的性质，每个迭代的质量因子单调改善。可以省略重新路由步骤，并且由互连网构成的边界框定义边。

74. 发明授权

US5835378A Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip 失效
标题翻译：用于集成电路芯片的电池放置中用于调平互连布线密度的计算机实现的方法
公开(公告)号：US5835378A
公开(公告)日：1998-11-10
申请号：US560834
申请日：1995-11-20
申请人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin , Douglas B. Boyle
发明人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin , Douglas B. Boyle
IPC分类号： G06F17/50 , G06F9/00 , G06F11/00
CPC分类号： G06F17/5072
摘要： A digital computer includes a processor, a memory and a program which operate in combination for inputting a placement of cells for an integrated circuit chip, and a netlist of wiring nets interconnecting the cells. The placement is divided into a plurality of contiguous regions, and cell densities in the regions are computed in accordance with locations of the cells in the placement. Wiring densities in the regions are computed in accordance with the locations of the cells and the netlist. The shapes of the regions are altered to produce altered regions such that cell densities and wiring densities in the altered regions are more level or uniform. The placement is then altered such that the cells occupy locations in the altered regions which are relative to their locations in the original regions. The porosities of the cells can also be computed and used in the computation of the region shapes. The wiring densities are computed by constructing bounding boxes around the wiring nets, and computing horizontal and vertical total heights and widths of bounding boxes that overlap the regions. The altered shapes are generated by computing optimal sizes for the regions for containing the cells and required interconnect wiring, computing new lengths for edges of the regions, and iteratively recomputing new positions for corners of the regions using a mechanical mass-spring model until the system reaches equilibrium.
摘要翻译：数字计算机包括处理器，存储器和程序，其组合操作用于输入用于集成电路芯片的单元的放置，以及互连单元的布线网的网表。放置被分成多个连续区域，并且根据放置中的单元格的位置来计算区域中的单元密度。根据单元格和网表的位置来计算区域中的布线密度。改变区域的形状以产生改变的区域，使得改变区域中的细胞密度和接线密度更高或均匀。然后改变放置，使得细胞占据相对于它们在原始区域中的位置的改变区域中的位置。还可以计算细胞的孔隙率，并用于计算区域形状。布线密度通过在布线网周围构造边界框，并计算与区域重叠的边界框的水平和垂直总高度和宽度来计算。改变的形状是通过计算用于包含单元的区域和所需的互连布线，计算区域边缘的新长度以及使用机械质量弹簧模型迭代地重新计算区域的角部的新位置而产生的，直到系统达到平衡。

75. 发明授权

US5834821A Triangular semiconductor "AND" gate device 失效
标题翻译：三角半导体“AND”门装置
公开(公告)号：US5834821A
公开(公告)日：1998-11-10
申请号：US517479
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L27/088 , H01L29/78
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在彼此成角度地移位60度的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

76. 发明授权

US5831863A Advanced modular cell placement system with wire length driven affinity system 失效
标题翻译：具有线长驱动亲和力系统的高级模块化放置系统
公开(公告)号：US5831863A
公开(公告)日：1998-11-03
申请号：US672725
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties.
摘要翻译：本文公开了一种用于确定与将位于半导体芯片的表面上的单元重新定位到表面上的不同位置的亲和度的系统。每个细胞可以是包含多个细胞的细胞网的一部分。系统最初定义了包含网络中包含单元格的所有单元格的边界框。然后，该系统基于边界框和包含单元格的区域的边界来建立惩罚向量，计算具有该单元作为成员的所有网络的归一化惩罚总和，并且基于标准化的惩罚总和来计算亲和度。

77. 发明授权

US5808330A Polydirectional non-orthoginal three layer interconnect architecture 失效
标题翻译：多向非正弦三层互连架构
公开(公告)号：US5808330A
公开(公告)日：1998-09-15
申请号：US517441
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/41 , H01L27/088
CPC分类号： G11C5/025 , G06F17/5072 , G06F17/5077 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , G03F1/36 , H01L29/0657 , H01L2924/0002
摘要： A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

78. 发明授权

US5789770A Hexagonal architecture with triangular shaped cells 失效
标题翻译：六角形结构与三角形细胞
公开(公告)号：US5789770A
公开(公告)日：1998-08-04
申请号：US517236
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L27/105 , H01L29/78
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

79. 发明授权

US5777360A Hexagonal field programmable gate array architecture 失效
标题翻译：六角场可编程门阵列架构
公开(公告)号：US5777360A
公开(公告)日：1998-07-07
申请号：US517508
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L27/088 , H01L27/115
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclose. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了使用六角形细胞的细胞结构。该体系结构不限于六角形细胞。细胞可以由两个或更多个六边形的簇由三角形，平行四边形以及能够适应各种细胞形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

80. 发明授权

US5699265A Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints 失效
标题翻译：物理设计自动化系统和设计集成电路芯片的过程，使用多路分区约束
公开(公告)号：US5699265A
公开(公告)日：1997-12-16
申请号：US525839
申请日：1995-09-08
申请人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A process for designing an integrated circuit chip includes specifying a set of cells, a set of wiring nets for interconnecting the cells, and a set of regions on the chip in which the cells are to be placed. An assignment of the cells of the set to the regions is generated, and the set of cells is randomly divided into a first subset of cells which remain in the assignment, and a second subset of cells which are removed from the assignment. Penalties are computed for assigning the cells of the second subset to the regions respectively, and the cells of the second subset are assigned to the regions such that a total penalty thereof is minimized. The process is repeated iteratively with the size of the second subset being progressively reduced relative to the size of the first subset until an end criterion is reached.
摘要翻译：设计集成电路芯片的过程包括指定一组单元，一组用于互连单元的布线网以及芯片上要放置单元的一组区域。生成集合到区域的单元的分配，并且将该组单元随机分成保留在分配中的单元的第一子集，以及从分配中移除的单元的第二子集。计算处罚以分配第二子集的细胞到区域，并且将第二子集的细胞分配给区域，使得其总惩罚最小化。迭代地重复该过程，相对于第一子集的大小，第二子集的大小逐渐减小，直到达到结束标准。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式