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71. 发明授权

US08278200B2 Metal-semiconductor intermixed regions 有权
标题翻译：金属半导体混合区域
公开(公告)号：US08278200B2
公开(公告)日：2012-10-02
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

72. 发明申请

US20120196424A1 METHOD OF FABRICATING A DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR 失效
标题翻译：深层金属（金属）绝缘子（MIM）电容器的制造方法
公开(公告)号：US20120196424A1
公开(公告)日：2012-08-02
申请号：US13017108
申请日：2011-01-31
申请人： Rishikesh Krishnan , Joseph F. Shepard, JR. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
发明人： Rishikesh Krishnan , Joseph F. Shepard, JR. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
IPC分类号： H01L21/02
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/1087 , H01L28/40 , H01L29/66181
摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.
摘要翻译：一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

73. 发明申请

US20120193729A1 DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES 失效
标题翻译：优化材料和材料替代金属结构结构的设备和方法
公开(公告)号：US20120193729A1
公开(公告)日：2012-08-02
申请号：US13017809
申请日：2011-01-31
申请人： TAKASHI ANDO , Christian Lavoie , Vijay Narayanan
发明人： TAKASHI ANDO , Christian Lavoie , Vijay Narayanan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/324 , H01L29/165 , H01L29/456 , H01L29/66606 , H01L29/66628 , H01L29/7848
摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.
摘要翻译：用于器件制造的器件和方法包括用牺牲材料形成栅极结构。硅化区域形成在与栅极结构相邻的源极/漏极区域上，或者形成在源极/漏极区域内的沟槽触点的底部。对源极/漏极区域或硅化物区域进行处理，以建立对后续热处理的阻力，并调整肖特基势垒高度，从而降低接触电阻。金属触点形成为与硅化物区域接触。去除牺牲材料并用替换导体代替。

74. 发明授权

US08168503B2 Method for forming an SOI schottky source/drain device to control encroachment and delamination of silicide 有权
标题翻译：用于形成SOI肖特基源极/漏极器件以控制硅化物侵蚀和分层的方法
公开(公告)号：US08168503B2
公开(公告)日：2012-05-01
申请号：US12726736
申请日：2010-03-18
申请人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
发明人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7839 , H01L29/78654
摘要： A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A raised semiconductor material is selectively formed on the first semiconductor layer adjacent to the gate structure. The raised semiconductor material is converted into Schottky source and drain regions composed of a metal semiconductor alloy. A non-reacted semiconductor material is present between the Schottky source and drain regions and the dielectric layer.
摘要翻译：提供一种制造肖特基场效应晶体管的方法，其包括提供具有覆盖在电介质层上的至少第一半导体层的衬底，其中第一半导体层具有小于10.0nm的厚度。栅极结构直接形成在第一半导体层上。凸起的半导体材料选择性地形成在与栅极结构相邻的第一半导体层上。凸起的半导体材料被转换成由金属半导体合金构成的肖特基源极和漏极区域。在肖特基源极和漏极区域与电介质层之间存在未反应的半导体材料。

75. 发明授权

US08003524B2 Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement 有权
标题翻译：电镀种子层包括用于屏障增强的氧/氮过渡区域
公开(公告)号：US08003524B2
公开(公告)日：2011-08-23
申请号：US12177309
申请日：2008-07-22
申请人： Chih-Chao Yang , Simon Gaudet , Christian Lavoie , Shom Ponoth , Terry A. Spooner
发明人： Chih-Chao Yang , Simon Gaudet , Christian Lavoie , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76856 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.
摘要翻译：提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。优选地，互连导电材料是Cu或AlCu。在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

76. 发明申请

US20110147809A1 FORMING A CARBON CONTAINING LAYER TO FACILITATE SILICIDE STABILITY IN A SILICON GERMANIUM MATERIAL 审中-公开
标题翻译：形成含硅层以提高硅锗材料中的硅氧烷稳定性
公开(公告)号：US20110147809A1
公开(公告)日：2011-06-23
申请号：US12644092
申请日：2009-12-22
申请人： Bin Yang , Devendra Sadana , Christian Lavoie , Ahmet Ozcan
发明人： Bin Yang , Devendra Sadana , Christian Lavoie , Ahmet Ozcan
IPC分类号： H01L29/78 , H01L21/20 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A method includes forming a silicon germanium layer, forming a layer comprising carbon and silicon on a top surface of the silicon germanium layer, forming a metal layer above the layer comprising carbon and silicon, and performing a thermal treatment to convert at least the layer comprising carbon and silicon to form a metal silicide layer.
摘要翻译：一种方法包括形成硅锗层，在硅锗层的顶表面上形成包含碳和硅的层，在包含碳和硅的层之上形成金属层，并进行热处理以至少将含有碳和硅以形成金属硅化物层。

77. 发明授权

US07932169B2 Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers 有权
标题翻译：使用无铅焊料进行倒装芯片的互连并具有改进的反应阻挡层
公开(公告)号：US07932169B2
公开(公告)日：2011-04-26
申请号：US12587301
申请日：2009-10-05
申请人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K Srivastava , Michael J. Sullivan
发明人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K Srivastava , Michael J. Sullivan
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05599 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/01083 , H01L2924/01049 , H01L2224/13099
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

78. 发明申请

US20110062525A1 METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR 有权
标题翻译：不同硅酸盐的方法和结构以及被提高或提高的源/排水以改善场效应晶体管
公开(公告)号：US20110062525A1
公开(公告)日：2011-03-17
申请号：US12560585
申请日：2009-09-16
申请人： Christian Lavoie , Viorel C. Ontalus , Ahmet S. Ozcan
发明人： Christian Lavoie , Viorel C. Ontalus , Ahmet S. Ozcan
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/28 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7848
摘要： A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.
摘要翻译：一种方法形成集成电路结构。该方法在第一类场效应晶体管上形成保护层，并从第二种场效应晶体管上方去除应力衬垫。然后，该方法从第二类型场效应晶体管的源极区和漏极区去除第一类型的硅化物层，但是将第一类型硅化物层的至少一部分留在第二类型场效应晶体管的栅极导体上。该方法在栅极导体和第二类场效应晶体管的源极和漏极区域上形成第二类型的硅化物层。所形成的第二类硅化物层与第一型硅化物层不同。例如，第一型硅化物层和第二类型硅化物层可以包括不同的材料，不同的厚度，不同的晶体取向和/或不同的化学相等。

79. 发明申请

US20100304563A1 MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS 有权
标题翻译：具有多个自对准硅化物接触的MOSFET结构
公开(公告)号：US20100304563A1
公开(公告)日：2010-12-02
申请号：US12814942
申请日：2010-06-14
申请人： Kevin K. Chan , Christian Lavoie , Kern Rim
发明人： Kevin K. Chan , Christian Lavoie , Kern Rim
IPC分类号： H01L21/283
CPC分类号： H01L29/66507 , H01L29/6653 , H01L29/7833
摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.
摘要翻译：提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

80. 发明申请

US20100003800A1 BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR 有权
标题翻译：双极晶体管，带有硅分集电极
公开(公告)号：US20100003800A1
公开(公告)日：2010-01-07
申请号：US12557557
申请日：2009-09-11
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.
摘要翻译：本发明的实施例提供一种制造半导体器件的方法。该方法包括在掺杂半导体材料层中限定子集电极区; 在所述掺杂半导体材料层的顶部上形成有源区，电介质区和到达区，所述电介质区将所述有源区与所述覆盖区分离; 并且将通过区域和子集电极区域的一部分硅化以形成部分硅化物的导电路径。还提供了由此制成的半导体器件。

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