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    • 72. 发明授权
    • Semiconductor integrated circuit achieving reliable data latching
    • 半导体集成电路实现可靠的数据锁存
    • US5952857A
    • 1999-09-14
    • US63439
    • 1998-04-21
    • Takaaki Suzuki
    • Takaaki Suzuki
    • G11C11/413G06F1/10G11C11/407H03K5/135H03K17/00H03L7/00H03L7/07H03L7/081H04L7/00H04L7/02H03K5/00H03K5/13
    • H03L7/0814H03K17/002H03K5/135H03L7/07H04L7/0012H04L7/0037H04L7/02H04L7/0041
    • A semiconductor integrated circuit receiving a plurality of input signals each exhibiting a signal-level change during a predetermined time span includes a timing-detection circuit which detects timing of said signal-level change of said input signals, and detects which input signal is furthest behind in terms of a signal-level-change timing among said plurality of input signals within said predetermined time span. The semiconductor integrated circuit further includes first delay-adjustment circuits which delay said plurality of input signals, respectively, in response to an output signal from the timing-detection circuit to generate delayed input signals such that signal-level-change timings of said delayed input signals are aligned to said signal-level-change timing of said furthest behind input signal, and latch circuits each latching a respective one of said delayed input signals at the same timing.
    • 接收在预定时间范围内呈现信号电平变化的多个输入信号的半导体集成电路包括检测所述输入信号的所述信号电平变化的定时的定时检测电路,并且检测哪个输入信号是最远的 在所述预定时间范围内的所述多个输入信号中的信号电平改变定时。 半导体集成电路还包括响应于来自定时检测电路的输出信号分别延迟所述多个输入信号的第一延迟调整电路,以产生延迟的输入信号,使得所述延迟输入的信号电平改变定时 信号与所述最远离输入信号的所述信号电平改变定时对准,并且每个锁存电路在相同的定时锁存相应的所述延迟的输入信号。
    • 75. 发明授权
    • Semiconductor integrated circuit device capable of reducing power
consumption
    • 半导体集成电路器件能够降低功耗
    • US5731720A
    • 1998-03-24
    • US784539
    • 1997-01-21
    • Takaaki SuzukiMakoto NiimiHideaki KawaiMasato Kaida
    • Takaaki SuzukiMakoto NiimiHideaki KawaiMasato Kaida
    • G11C11/401G11C11/407H01L21/822H01L27/04H01L27/10H03K19/00H03K17/30
    • H03K19/0013
    • A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption. In the semiconductor integrated circuit device comprising: a current path which is formed between a predetermined power source terminal (or a predetermined power source pad) and a predetermined low potential power source line, a comparison circuit for comparing a node potential in the current path with a predetermined threshold voltage to thereby detect whether the voltage applied to said power source terminal is a voltage which is larger than an upper limit value of the terminal voltage, a signal generation circuit for generating a predetermined logic signal when the states of some designated control terminals satisfy a combination which is determined in advance, if the logic state of an output signal of said signal generation circuit is a predetermined logic state when said comparison circuit has detected that the voltage applied to the power source terminal is a voltage which is larger than an upper limit value of the terminal voltage, a circuit equipped with a predetermined function mounted on the chip is activated, the semiconductor integrated circuit device being characterized by comprising ON/OFF circuit for turning on and off said current path in accordance with the logic state of the output signal of said signal generation circuit.
    • 半导体集成电路器件旨在防止不必要的泄漏电流的产生,从而降低功耗。 在半导体集成电路装置中,包括:形成在预定电源端子(或预定电源焊盘)和预定低电位电源线之间的电流路径,用于将当前路径中的节点电位与 预定的阈值电压,从而检测施加到所述电源端子的电压是否是大于端子电压的上限值的电压;当一些指定的控制端子的状态产生预定逻辑信号的信号产生电路 如果所述信号发生电路的输出信号的逻辑状态是预定的逻辑状态,当所述比较电路检测到施加到电源端子的电压是大于电源端的电压时,满足预先确定的组合 端子电压的上限值,配备有预定功能的电路 n的半导体集成电路装置的特征在于包括根据所述信号发生电路的输出信号的逻辑状态接通和断开所述电流路径的ON / OFF电路。