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71. 发明申请

US20130193445A1 SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC 审中-公开
公开(公告)号：US20130193445A1
公开(公告)日：2013-08-01
申请号：US13359110
申请日：2012-01-26
申请人： Robert H. Dennard , Alfred Grill , Effendi Leobandung , Deborah A. Neumayer , Dea-Gyu Park , Ghavam G. Shahidi , Leathen Shi
发明人： Robert H. Dennard , Alfred Grill , Effendi Leobandung , Deborah A. Neumayer , Dea-Gyu Park , Ghavam G. Shahidi , Leathen Shi
IPC分类号： H01L29/06 , H01L21/30 , H01L29/12 , H01L29/16 , H01L29/20
CPC分类号： H01L29/78603 , H01L21/02112 , H01L21/02274 , H01L21/0228 , H01L21/76254
摘要： Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect.

72. 发明申请

US20130154005A1 SOI FINFET WITH RECESSED MERGED FINS AND LINER FOR ENHANCED STRESS COUPLING 有权
标题翻译：具有残余的合并FINS和衬垫的SOI FINFET用于增强应力耦合
公开(公告)号：US20130154005A1
公开(公告)日：2013-06-20
申请号：US13606893
申请日：2012-09-07
申请人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/12
CPC分类号： H01L29/7843 , H01L29/6656 , H01L29/66795
摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SW substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.
摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。一种方法包括：向SW基板提供翅片，在翅片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并翅片，在栅极周围沉积虚拟间隔物，以及将合并的外延膜。然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。垂直硅化物提高了耐扩散性。

73. 发明授权

US07723750B2 MOSFET with super-steep retrograded island 失效
标题翻译：具超级陡峭退火岛的MOSFET
公开(公告)号：US07723750B2
公开(公告)日：2010-05-25
申请号：US11774221
申请日：2007-07-06
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L29/737
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。

74. 发明授权

US07442993B2 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
标题翻译：通过弹性应变转移形成的超薄，高品质应变绝缘体上的绝缘体
公开(公告)号：US07442993B2
公开(公告)日：2008-10-28
申请号：US11293774
申请日：2005-12-02
申请人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
发明人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

75. 发明申请

US20080179636A1 N-FETS WITH TENSILELY STRAINED SEMICONDUCTOR CHANNELS, AND METHOD FOR FABRICATING SAME USING BURIED PSEUDOMORPHIC LAYERS 审中-公开
标题翻译：具有拉伸半导体通道的N-FET以及使用BURIED PSEUDOMORPHIC层的相同方法
公开(公告)号：US20080179636A1
公开(公告)日：2008-07-31
申请号：US11307224
申请日：2007-01-27
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
IPC分类号： H01L29/04 , H01L21/335 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7849
摘要： The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.
摘要翻译：本发明涉及各自包含应变半导体通道的高性能n沟道场效应晶体管（n-FET），以及通过使用包含假象形成的压缩应变的掩埋伪晶层来形成这种n-FET的方法。

76. 发明申请

US20080113507A1 POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE 失效
标题翻译：多晶硅衬底接触SOI结构
公开(公告)号：US20080113507A1
公开(公告)日：2008-05-15
申请号：US12014127
申请日：2008-01-15
申请人： David Dobuzinsky , Byeong Kim , Effendi Leobandung , Munir Naeem , Brian Tessier
发明人： David Dobuzinsky , Byeong Kim , Effendi Leobandung , Munir Naeem , Brian Tessier
IPC分类号： H01L21/441
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

77. 发明授权

US07354806B2 Semiconductor device structure with active regions having different surface directions and methods 有权
标题翻译：具有不同表面方向和方法的有源区的半导体器件结构
公开(公告)号：US07354806B2
公开(公告)日：2008-04-08
申请号：US10711416
申请日：2004-09-17
申请人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
发明人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
IPC分类号： H01L21/00
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译：公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个其他。

78. 发明申请

US20070252203A1 STRUCTURE AND METHOD FOR MANUFACTURING MOSFET WITH SUPER-STEEP RETROGRADED ISLAND 失效
标题翻译：具有超级退化岛的MOSFET制造结构和方法
公开(公告)号：US20070252203A1
公开(公告)日：2007-11-01
申请号：US11774221
申请日：2007-07-06
申请人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda Mocuta , Dan Mocuta
IPC分类号： H01L29/78
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffisivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

79. 发明授权

US07288451B2 Method and structure for forming self-aligned, dual stress liner for CMOS devices 失效
标题翻译：用于形成CMOS器件自对准双应力衬垫的方法和结构
公开(公告)号：US07288451B2
公开(公告)日：2007-10-30
申请号：US10906669
申请日：2005-03-01
申请人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
发明人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L29/6653 , H01L29/7843 , Y10S438/938
摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.
摘要翻译：用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度表面。除去侧壁表面上的第二类型应力衬垫的部分，并且去除第一极性类型装置上的第二类型应力衬垫的部分。

80. 发明申请

US20060199326A1 METHOD AND STRUCTURE FOR FORMING SELF-ALIGNED, DUAL STRESS LINER FOR CMOS DEVICES 失效
标题翻译：用于形成用于CMOS器件的自对准双重应力衬垫的方法和结构
公开(公告)号：US20060199326A1
公开(公告)日：2006-09-07
申请号：US10906669
申请日：2005-03-01
申请人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
发明人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L29/6653 , H01L29/7843 , Y10S438/938
摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the
摘要翻译：用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度表面。去除侧壁表面上的第二类应力衬垫的部分，并且将第二类型应力衬垫的部分移出

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