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71. 发明授权

US07989307B2 Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same 有权
标题翻译：在半导体结构中形成隔离的有源区，沟槽和导电线的方法以及包括其的半导体结构
公开(公告)号：US07989307B2
公开(公告)日：2011-08-02
申请号：US12114932
申请日：2008-05-05
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L21/00
CPC分类号： H01L29/0653 , H01L21/2815 , H01L21/3086 , H01L21/3088 , H01L27/0207 , H01L27/0886 , H01L27/108 , H01L27/10876 , H01L27/10891 , H01L29/0649 , H01L29/4236 , H01L29/66621 , H01L29/66795
摘要： Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.
摘要翻译：公开了不对称特征和包括其的半导体结构的间距倍增方法。在一个实施例中，可以使用单个光刻掩模来扩展例如DRAM阵列的三重特征。在一个实施例中，两个字线和接地栅极可以是倍频。还公开了包括这些特征的半导体结构。

72. 发明授权

US07700441B2 Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates 有权
标题翻译：形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，包括晶体管栅极阵列和门阵列外围的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极和第二接地隔离门
公开(公告)号：US07700441B2
公开(公告)日：2010-04-20
申请号：US11346914
申请日：2006-02-02
申请人： Young Pil Kim , Kunal R. Parekh
发明人： Young Pil Kim , Kunal R. Parekh
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823456 , H01L21/823487 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，该集成电路包括晶体管栅极阵列和外围于栅极阵列的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极和第二接地隔离门。在一个实施方案中，形成场效应晶体管的方法包括在衬底的半导体材料上形成掩模材料。通过掩模材料形成沟槽并进入半导体材料。栅介电材料形成在半导体材料的沟槽内。栅极材料沉积在掩模材料中的沟槽内并且在半导体材料中的沟槽内沉积在栅极电介质材料上。形成源/漏区。考虑了其他方面和实现。

73. 发明申请

US20090224299A1 METHOD AND APPARATUS FOR PROVIDING AN INTEGRATED CIRCUIT HAVING P AND N DOPED GATES 有权
标题翻译：用于提供P型和N型栅极的集成电路的方法和装置
公开(公告)号：US20090224299A1
公开(公告)日：2009-09-10
申请号：US12467896
申请日：2009-05-18
申请人： Chandra Mouli , Kunal R. Parekh
发明人： Chandra Mouli , Kunal R. Parekh
IPC分类号： H01L31/112 , H01L27/088
CPC分类号： H01L21/823842 , H01L21/28202 , H01L21/823857 , H01L27/14689 , H01L29/518
摘要： A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and nitrogen concentrations and gate electrodes with differing conductivity types and active dopant concentrations.
摘要翻译：一种提供集成电路的方法和装置，该集成电路具有多个具有不同厚度和氮浓度的栅极氧化物层的栅叠层结构，以及具有不同导电类型和活性掺杂浓度的栅电极。

74. 发明授权

US07462534B2 Methods of forming memory circuitry 有权
标题翻译：形成存储器电路的方法
公开(公告)号：US07462534B2
公开(公告)日：2008-12-09
申请号：US11196051
申请日：2005-08-02
申请人： Kunal R. Parekh , Suraj Mathew , Steve Cole
发明人： Kunal R. Parekh , Suraj Mathew , Steve Cole
IPC分类号： H01L21/8244
CPC分类号： H01L29/6656 , H01L27/10882 , H01L27/10891 , H01L27/10894
摘要： The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成存储器电路的方法。在一个实现中，提供了具有存储器阵列电路区域和外围电路区域的衬底。存储器阵列电路区域包括具有第一最小线间距的晶体管栅极线。外围电路区域包括具有大于第一最小线间距的第二最小线间距的晶体管栅极线。在存储器阵列区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物之前，在外围电路区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物。考虑了其他方面和实现。

75. 发明申请

US20080280409A1 Memory Arrays, Semiconductor Constructions And Electronic Systems; And Methods Of Forming Memory Arrays, Semiconductor Constructions And Electronic Systems 有权
标题翻译：存储阵列，半导体结构和电子系统; 和存储阵列，半导体结构和电子系统的形成方法
公开(公告)号：US20080280409A1
公开(公告)日：2008-11-13
申请号：US11745783
申请日：2007-05-08
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： H01L21/336 , H01L21/44 , H01L27/108 , H01L29/76
CPC分类号： H01L29/78 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/10873 , H01L27/1207 , H01L29/0603 , H01L29/7841
摘要： Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
摘要翻译：一些实施例包括具有在SOI上部分延伸的晶体管栅极的DRAM以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点的电容器。一些实施例包括具有完全在SOI上的晶体管栅极的OC1T存储器，以及形成这种0C1T存储器的方法。

76. 发明授权

US07442977B2 Gated field effect devices 失效
标题翻译：门控场效应器件
公开(公告)号：US07442977B2
公开(公告)日：2008-10-28
申请号：US11253461
申请日：2005-10-19
申请人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
发明人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
IPC分类号： H01L27/108
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

77. 发明授权

US07411255B2 Dopant barrier for doped glass in memory devices 有权
标题翻译：存储器件中掺杂玻璃的掺杂阻挡层
公开(公告)号：US07411255B2
公开(公告)日：2008-08-12
申请号：US11003138
申请日：2004-12-03
申请人： Kunal R. Parekh , Gurtej Singh Sandhu
发明人： Kunal R. Parekh , Gurtej Singh Sandhu
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L21/28247 , H01L21/3003 , H01L21/76832
摘要： A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.
摘要翻译：半导体器件具有在掺杂的玻璃层和形成在衬底上的表面结构之间形成的扩散阻挡层。扩散阻挡层包括氧化铝和任选的氮化物，并且具有满足表面结构之间的间隙的高纵横比的层厚度，同时充分防止掺杂的玻璃层中的掺杂剂从掺杂的玻璃层扩散到表面结构，并且基质。此外，在形成氧化铝期间可以使用重水，使得可以在表面结构和基底的界面附近实现氘，以增强器件的性能。

78. 发明授权

US07384849B2 Methods of forming recessed access devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关联的凹陷接入设备的方法
公开(公告)号：US07384849B2
公开(公告)日：2008-06-10
申请号：US11090529
申请日：2005-03-25
申请人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
发明人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.
摘要翻译：本发明包括形成凹入进入装置的方法。提供基板以在其中具有凹入的接入装置沟槽。一对凹进的接入设备沟槽彼此相邻。导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

79. 发明授权

US07315074B2 Use of DAR coating to modulate the efficiency of laser fuse blows 有权
标题翻译：使用DAR涂层来调节激光熔丝的效率
公开(公告)号：US07315074B2
公开(公告)日：2008-01-01
申请号：US11140859
申请日：2005-05-31
申请人： Mark Fischer , Zhiping Yin , Thomas R. Glass , Kunal R. Parekh , Gurtej Singh Sandhu
发明人： Mark Fischer , Zhiping Yin , Thomas R. Glass , Kunal R. Parekh , Gurtej Singh Sandhu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
摘要翻译：本发明涉及一种激光熔丝。激光熔丝包括包含导热材料的元件。保险丝还包括吸收元件，该吸收元件包括具有与热传导元件重叠的热或光吸收的可调节容量的材料。保险丝还包括覆盖并包围导热元件和吸收元件的外绝缘元件。

80. 发明授权

US07268384B2 Semiconductor substrate having first and second pairs of word lines 有权
标题翻译：半导体衬底具有第一和第二对字线
公开(公告)号：US07268384B2
公开(公告)日：2007-09-11
申请号：US11292028
申请日：2005-12-01
申请人： Kunal R. Parekh , Byron N. Burgess
发明人： Kunal R. Parekh , Byron N. Burgess
IPC分类号： H01L29/17 , H01L27/84 , H01L27/75 , H01L27/85 , H01L27/86 , H01L27/88 , H01L27/90 , H01L27/91 , H01L27/97
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
摘要翻译：本发明包括形成存储器电路的方法。在一个实施方案中，半导体衬底包括一对在其间接收的位节点的字线。在位节点上的绝缘材料内形成位节点接触开口。牺牲性封堵材料形成在一对字线之间的位节点接触开口内。牺牲性封堵材料从一对字线对之间的位节点接触开口移除，并由与位节点电连接的导电材料代替。之后，将导电材料形成为位线。

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