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71. 发明授权

US5786256A Method of reducing MOS transistor gate beyond photolithographically patterned dimension 失效
标题翻译：减少MOS晶体管栅极超过光刻图案尺寸的方法
公开(公告)号：US5786256A
公开(公告)日：1998-07-28
申请号：US684407
申请日：1996-07-19
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/66583 , H01L21/28123
摘要： A semiconductor fabrication process for fabricating MOS transistors in which dielectric spacer structures are used prior to gate formation to reduce the gate length below the minimum feature size resolvable by the photolithography equipment. A semiconductor substrate having a channel region laterally disposed between a pair of source/drain regions is provided. A dielectric stack is formed on an upper surface of the semiconductor substrate and patterned to expose an upper surface of a spacer region of the semiconductor substrate. The spacer region includes the channel region and peripheral portions of the pair of source/drain regions proximal to the channel region. The patterning of the dielectric stack results in the formation of a pair of opposing sidewalls in the dielectric stack. Thereafter, a pair of first spacer structures are formed on the pair of opposing sidewalls such that the pair of first spacer structures cover or shadow the peripheral portions of the source/drain regions and such that an upper surface of the channel region is exposed. A gate structure is then formed on the upper surface of the channel region. The gate structure is laterally disposed between the pair of first spacer structures. A first dopant species is then introduced into the source/drain regions of the semiconductor substrate.
摘要翻译：一种用于制造MOS晶体管的半导体制造工艺，其中在栅极形成之前使用电介质间隔物结构以将栅极长度减小到低于由光刻设备可分辨的最小特征尺寸。提供具有横向设置在一对源/漏区之间的沟道区的半导体衬底。在半导体衬底的上表面上形成电介质叠层，并将其图案化以暴露半导体衬底的间隔区域的上表面。间隔区域包括通道区域和靠近通道区域的一对源极/漏极区域的外围部分。电介质堆叠的图案化导致在电介质叠层中形成一对相对的侧壁。此后，一对第一间隔结构形成在一对相对的侧壁上，使得该对第一间隔结构覆盖或遮蔽源极/漏极区的周边部分，并且使得沟道区的上表面露出。然后在沟道区域的上表面上形成栅极结构。栅极结构横向设置在该对第一间隔结构之间。然后将第一掺杂剂物质引入到半导体衬底的源极/漏极区域中。

72. 发明授权

US5648286A Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region 失效
标题翻译：制造具有轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的不对称晶体管的方法
公开(公告)号：US5648286A
公开(公告)日：1997-07-15
申请号：US711383
申请日：1996-09-03
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66659 , H01L29/7835
摘要： An asymmetrical IGFET including a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.
摘要翻译：公开了一种包括轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的非对称IGFET。优选地，轻掺杂漏极区域和重掺杂源极区域提供通道结。制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以将轻掺杂源区域分成重掺杂源区，而不掺杂轻掺杂漏极区，分别与第一和第二侧壁相邻形成第一和第二间隔，并施加第三离子注入以将重掺杂源区的一部分转换到外部所述第一间隔物进入超重掺杂源区，而不掺杂所述第一间隔物下方的重掺杂源区的一部分，以及将所述第二间隔区外部的所述轻掺杂漏极区的一部分转换为重掺杂漏极区，而不掺杂第二间隔物下方的轻掺杂漏极区的部分。有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

73. 发明授权

US06380554B1 Test structure for electrically measuring the degree of misalignment between successive layers of conductors 失效
标题翻译：用于电测量连续导体层之间的未对准程度的测试结构
公开(公告)号：US06380554B1
公开(公告)日：2002-04-30
申请号：US09093358
申请日：1998-06-08
申请人： John J. Bush , H. Jim Fulford, Jr. , Mark I. Gardner
发明人： John J. Bush , H. Jim Fulford, Jr. , Mark I. Gardner
IPC分类号： H01L2358
CPC分类号： G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/3011
摘要： The present invention advantageously provides a test structure and method for using electrical measurements to determine the overlay between successive layers of conductors lithographically patterned upon a semiconductor topography. According to an embodiment, a test structure is provided which includes first, second, and third conductive structures having first, second, and third corner regions, respectively. Alternatively, the conductive structures may include only a single conductive structure having three corner regions. Each corner region is bounded by a pair of outer lateral edges configured substantially perpendicular to one another. First, second, and third conductors are operably coupled to the first, second, and third corner regions, respectively, such that overlapping areas of the conductors arranged directly above the corner regions are substantially rectangular in shape. The layout design for the test structure specifies the targeted dimensions, x and y, of each overlapping area. Fabrication of the test structure may result in the overlapping areas being shifted from their targeted positions such that their dimensions are larger or smaller than their targeted values. The amount by which the overlapping areas are shifted in the x direction is known as &Dgr;x, and the amount by which the overlapping areas are shifted in the y direction is known as &Dgr;y. The contact resistances between the overlapping areas of the conductors and the corner regions may be found and substituted into equations for &Dgr;x and &Dgr;y.
摘要翻译：本发明有利地提供了一种测试结构和方法，用于使用电测量来确定在半导体拓扑图上光刻图案化的导体的连续层之间的叠层。根据一个实施例，提供一种测试结构，其包括分别具有第一，第二和第三角区域的第一，第二和第三导电结构。或者，导电结构可以仅包括具有三个拐角区域的单个导电结构。每个拐角区域由基本上彼此垂直配置的一对外侧边缘限定。第一，第二和第三导体分别可操作地耦合到第一，第二和第三拐角区域，使得直接布置在拐角区域上方的导体的重叠区域基本上是矩形的。测试结构的布局设计指定每个重叠区域的目标尺寸x和y。测试结构的制造可能导致重叠区域从其目标位置偏移，使得其尺寸大于或小于其目标值。重叠区域在x方向上偏移的量被称为DELTAx，并且重叠区域在y方向上偏移的量被称为DELTAY。可以找到导体和拐角区域的重叠区域之间的接触电阻，并将其代入DELTAx和DELTAY的等式。

74. 发明授权

US06372588B2 Method of making an IGFET using solid phase diffusion to dope the gate, source and drain 失效
标题翻译：使用固相扩散制造IGFET以掺杂栅极，源极和漏极的方法
公开(公告)号：US06372588B2
公开(公告)日：2002-04-16
申请号：US08837523
申请日：1997-04-21
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/2256 , H01L21/32155 , H01L29/665
摘要： A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.
摘要翻译：公开了使用固相扩散制造IGFET的方法。该方法包括在半导体衬底中提供器件区域，在器件区域上形成栅极绝缘体，在栅极绝缘体上形成栅极，在栅极和器件区域上形成绝缘层，在其上形成重掺杂扩散源层绝缘层，并且通过固相扩散将掺杂剂从扩散源层驱动通过绝缘层进入栅极和器件区域，从而大量掺杂栅极并在器件区域中形成重掺杂的源极和漏极。优选地，栅极和扩散源层是多晶硅，栅绝缘体和绝缘层是二氧化硅，掺杂剂是硼或硼物质，并且掺杂剂为栅极，源极和漏极提供基本上所有的P型掺杂，从而提供浅通道结并且减少或消除从孔进入衬底的硼渗透。

75. 发明授权

US06326251B1 Method of making salicidation of source and drain regions with metal gate MOSFET 有权
标题翻译：用金属栅极MOSFET对源极和漏极区域进行腐蚀的方法
公开(公告)号：US06326251B1
公开(公告)日：2001-12-04
申请号：US09290790
申请日：1999-01-12
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28079 , H01L21/28088 , H01L21/823814 , H01L21/823835 , H01L29/495 , H01L29/66545
摘要： A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.
摘要翻译：形成晶体管的方法包括在刚刚形成衬底上的隔离和有源区域之后的初始处理阶段中形成源极/漏极注入。在介电层顶部的衬底的表面上形成均匀的氮化物层。然后沉积硅化物金属并与下面的硅反应以在源区和漏区上形成自对准硅化物。然后在硅化物的顶部上形成第二电介质层，并且形成为相对于氮化物层是选择性的。此后，去除氮化物层，然后形成最终的栅极电介质。最后，在栅极电介质的顶部形成金属栅极导体。仅在执行所有退火步骤之后才形成金属栅极导体，以防止金属通过栅极电介质尖峰，从而破坏器件。

76. 发明授权

US06297535B1 Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection 有权
标题翻译：晶体管具有基本上耐漏极侧热载流子注入的栅电介质
公开(公告)号：US06297535B1
公开(公告)日：2001-10-02
申请号：US09510096
申请日：2000-02-22
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L31119
CPC分类号： H01L29/66659 , H01L21/28176 , H01L21/28194 , H01L29/518 , H01L29/6659 , H01L29/7833 , Y10S257/90 , Y10S438/91
摘要： A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. An LDD implant is performed to lightly dope the source-side and drain-side junctions. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor. The unmasked portions of the source-side and drain-side junctions are heavily doped, resulting in source and drain regions that are aligned to the exposed lateral edges of the spacers. The drain-side spacer is removed and barrier atoms are forwarded through the exposed etch stop material and into a substrate/gate oxide interface region near the drain junction. The barrier atoms help reduce hot electron effects by blocking diffusion avenues of carriers (holes or electrons) from the drain-side junction into the gate oxide.
摘要翻译：提供了一种晶体管制造工艺，该方法得益于将栅极原子结合在晶体管的栅极氧化物附近在漏极附近的优点。为了形成晶体管，首先在硅基衬底上生长栅氧化层。然后在栅极氧化物层上沉积多晶硅层。去除多晶硅层和氧化物层的部分以形成栅极导体和栅极氧化物，从而暴露衬底内的源极侧和漏极侧结。进行LDD注入以轻轻地掺杂源极侧漏极和漏极侧结。蚀刻停止材料可以形成在栅极导体的相对的侧壁表面，栅极导体的上表面以及源极侧和漏极侧结。然后可以在位于栅极导体的侧壁表面上的蚀刻停止材料的横向邻近地形成间隔。源侧和漏极侧结的未屏蔽部分被重掺杂，导致源极和漏极区域与间隔物的暴露的侧向边缘对准。去除漏极侧隔离物，并且阻挡原子通过暴露的蚀刻停止材料并且进入到漏极结附近的衬底/栅极氧化物界面区域中。阻挡原子有助于通过阻止载流子（空穴或电子）从漏极侧结到扩散通道到栅极氧化物中来减少热电子效应。

77. 发明授权

US06274442B1 Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same 失效
标题翻译：具有氮的外延生长栅电介质的晶体管及其制造方法
公开(公告)号：US06274442B1
公开(公告)日：2001-08-14
申请号：US09116417
申请日：1998-07-15
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably nitrogen atoms, within a barrier layer. The barrier layer is interposed between the gate dielectric and the semiconductor substrate. The barrier layer serves to inhibit the passage of dopants from the gate conductor into the channel area. The barrier layer is preferably a nitrogen doped silicon epitaxial layer. The barrier layer may be composed of two layers, a silicon epitaxial layer and a nitrogen doped epitaxial layer formed upon the silicon epitaxial layer.
摘要翻译：提供集成电路制造方法，用于在屏障层内并入屏障原子，优选氮原子。阻挡层介于栅电介质和半导体衬底之间。阻挡层用于抑制掺杂剂从栅极导体进入沟道区的过程。阻挡层优选为氮掺杂硅外延层。阻挡层可以由两层构成，硅外延层和形成在硅外延层上的氮掺杂外延层。

78. 发明授权

US06259142B1 Multiple split gate semiconductor device and fabrication method 失效
标题翻译：多分裂栅极半导体器件及其制造方法
公开(公告)号：US06259142B1
公开(公告)日：2001-07-10
申请号：US09056837
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2976
CPC分类号： H01L29/66484 , H01L29/7831
摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.
摘要翻译：具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

79. 发明授权

US06239476B1 Integrated circuit isolation structure employing a protective layer and method for making same 有权
标题翻译：采用保护层的集成电路隔离结构及其制造方法
公开(公告)号：US06239476B1
公开(公告)日：2001-05-29
申请号：US09176132
申请日：1998-10-21
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A trench surface boundary is defined where the trench sidewalls intersect the upper surface of the semiconductor substrate. The trench may be filled with a trench fill material. A protective layer is then formed above the trench. The protective layer covers the trench and laterally extends above the semiconductor substrate at least a first distance beyond the trench surface boundaries.
摘要翻译：提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。限定沟槽表面边界，其中沟槽侧壁与半导体衬底的上表面相交。沟槽可以填充沟槽填充材料。然后在沟槽上方形成保护层。保护层覆盖沟槽并横向延伸超过沟槽表面边界至少第一距离半导体衬底上方。

80. 发明授权

US06218720B1 Semiconductor topography employing a nitrogenated shallow trench isolation structure 有权
标题翻译：半导体地形采用氮化浅沟槽隔离结构
公开(公告)号：US06218720B1
公开(公告)日：2001-04-17
申请号：US09176131
申请日：1998-10-21
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
IPC分类号： H01L2900
CPC分类号： H01L21/76224 , H01L21/3145 , H01L21/3185
摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.
摘要翻译：提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。主要包括氮化物的衬垫形成在沟槽底板和侧壁上。然后将衬里氧化。沟槽电介质可以形成在沟槽内并且被平坦化以完成隔离结构。

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