专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20070091706A1 MEMORY REDUNDANCY PROGRAMMING 审中-公开
标题翻译：记忆冗余编程
公开(公告)号：US20070091706A1
公开(公告)日：2007-04-26
申请号：US11565439
申请日：2006-11-30
申请人： Kunal Parekh
发明人： Kunal Parekh
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C29/789
摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.
摘要翻译：提供了一种用于执行冗余编程的方法和装置。本发明的系统包括用于执行存储器测试的设备测试单元。该系统还包括可操作地耦合到设备测试单元的存储器件。存储器件包括存取晶体管，其包括电荷捕获区域。在电荷俘获单元中捕获电荷时修改存取晶体管的阈值电压。存储器件还包括存储器元件和与存储器元件相关联的保险丝。响应于修改存取晶体管的阈值电压，熔丝能够进入替代状态。熔丝的状态可用于对存储元件进行编程或解除编程。

72. 发明申请

US20070032011A1 Methods of forming memory circuitry 有权
标题翻译：形成存储器电路的方法
公开(公告)号：US20070032011A1
公开(公告)日：2007-02-08
申请号：US11196051
申请日：2005-08-02
申请人： Kunal Parekh , Suraj Mathew , Steve Cole
发明人： Kunal Parekh , Suraj Mathew , Steve Cole
IPC分类号： H01L21/8244
CPC分类号： H01L29/6656 , H01L27/10882 , H01L27/10891 , H01L27/10894
摘要： The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成存储器电路的方法。在一个实现中，提供了具有存储器阵列电路区域和外围电路区域的衬底。存储器阵列电路区域包括具有第一最小线间距的晶体管栅极线。外围电路区域包括具有大于第一最小线间距的第二最小线间距的晶体管栅极线。在存储器阵列区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物之前，在外围电路区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物。考虑了其他方面和实现。

73. 发明申请

US20060152601A1 Low cost digital camera with one-time programmable memory 审中-公开
标题翻译：低成本数码相机配备一次性可编程存储器
公开(公告)号：US20060152601A1
公开(公告)日：2006-07-13
申请号：US11034000
申请日：2005-01-13
申请人： Kunal Parekh
发明人： Kunal Parekh
IPC分类号： H04N5/76
CPC分类号： H04N5/335
摘要： The present invention relates to a digital camera having an imager pixel array and memory for storing images from the array, the memory is programmable to non-rewritably store images for subsequent readout. The non-rewritable memory storage permits a low cost image storage enabling the camera to be disposable or reconditioned for reuse.
摘要翻译：本发明涉及具有成像器像素阵列的数字照相机和用于存储来自阵列的图像的存储器，该存储器是可编程的，以不可重写地存储图像用于随后的读出。不可重写存储器存储器允许低成本的图像存储，使得相机能够被一次性或重新调整以便重新使用。

74. 发明申请

US20060121677A1 Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors 有权
标题翻译：形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法
公开(公告)号：US20060121677A1
公开(公告)日：2006-06-08
申请号：US11003275
申请日：2004-12-03
申请人： Kunal Parekh , John Zahurak
发明人： Kunal Parekh , John Zahurak
IPC分类号： H01L21/8234
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823425 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
摘要翻译：本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与在晶体管的栅极附近的各向异性蚀刻的侧壁间隔开。

75. 发明申请

US20060043468A1 Stepped gate configuration for non-volatile memory 审中-公开
公开(公告)号：US20060043468A1
公开(公告)日：2006-03-02
申请号：US11257843
申请日：2005-10-25
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , G11C16/0416 , G11C16/0483 , H01L29/40117
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

76. 发明申请

US20060038244A1 Gated field effect devices 失效
标题翻译：门控场效应器件
公开(公告)号：US20060038244A1
公开(公告)日：2006-02-23
申请号：US11253461
申请日：2005-10-19
申请人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
发明人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
IPC分类号： H01L29/94
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

77. 发明申请

US20050255701A1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20050255701A1
公开(公告)日：2005-11-17
申请号：US10848247
申请日：2004-05-17
申请人： Werner Juengling , Steven McDonald , Kunal Parekh
发明人： Werner Juengling , Steven McDonald , Kunal Parekh
IPC分类号： H01L21/302 , H01L23/525
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.
摘要翻译：本发明包括一种方法，通过该方法制造半导体结构的保险丝盒以在其中延伸的保险丝上具有基本均匀的层。在具体方面，本发明包括这样的方法，其中与保险丝盒区域同时进行与接合焊盘和再分配层的制造和图案相关联的一个或多个处理步骤，以形成和/或去除直接位于保险丝盒区域上方的材料。

78. 发明申请

US20050173745A1 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures 有权
标题翻译：电容器结构，DRAM单元结构和集成电路，以及形成电容器结构，集成电路和DRAM单元结构的方法
公开(公告)号：US20050173745A1
公开(公告)日：2005-08-11
申请号：US11074107
申请日：2005-03-07
申请人： Kunal Parekh , John Zahurak
发明人： Kunal Parekh , John Zahurak
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10811 , H01L27/10855 , H01L28/84 , Y10S438/964
摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.
摘要翻译：本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。本发明包括形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。

79. 发明申请

US20050162963A1 Memory redundancy programming 失效
标题翻译：内存冗余编程
公开(公告)号：US20050162963A1
公开(公告)日：2005-07-28
申请号：US10764954
申请日：2004-01-26
申请人： Kunal Parekh
发明人： Kunal Parekh
IPC分类号： G11C11/34 , G11C29/00
CPC分类号： G11C17/18 , G11C29/789
摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.
摘要翻译：提供了一种用于执行冗余编程的方法和装置。本发明的系统包括用于执行存储器测试的设备测试单元。该系统还包括可操作地耦合到设备测试单元的存储器件。存储器件包括存取晶体管，其包括电荷捕获区域。在电荷俘获单元中捕获电荷时修改存取晶体管的阈值电压。存储器件还包括存储器元件和与存储器元件相关联的保险丝。响应于修改存取晶体管的阈值电压，熔丝能够进入替代状态。熔丝的状态可用于对存储元件进行编程或解除编程。

80. 发明申请

US20050030697A1 CAPACITOR STRUCTURE 失效
标题翻译：电容结构
公开(公告)号：US20050030697A1
公开(公告)日：2005-02-10
申请号：US10932503
申请日：2004-09-02
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L21/02 , H01L21/8242 , H01G4/30
CPC分类号： H01L27/10852 , H01L28/82
摘要： A capacitor is formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
摘要翻译：电容器形成为具有大致凹入的形状并且具有可选的折叠或回旋表面。凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。电容器以与电致密DRAM阵列一致的微电子方式制造。制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式