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71. 发明申请

US20080183222A1 PEDICLE SCREW AND OPERATING DEVICE THEREOF 有权
标题翻译： PEDICLE螺丝及其操作装置
公开(公告)号：US20080183222A1
公开(公告)日：2008-07-31
申请号：US12061326
申请日：2008-04-02
申请人： Keun Ho Park , Jong Myeon Choi , Hoon Lee
发明人： Keun Ho Park , Jong Myeon Choi , Hoon Lee
IPC分类号： A61B17/56
CPC分类号： A61B17/7032 , A61B17/7089 , A61B17/864
摘要： Disclosed is a spine fixation apparatus, more particularly, a pedicle screw implanted into a spine and an operating device for the pedicle screw capable of easily inserting a rod to a head section of the pedicle screw in order to securely fix the spine. The pedicle screw has a head section including a recess part defined by first and second sidewalls, a screw section, and a support unit formed at an upper portion of the recess part of the head section while connecting the first sidewall to the second sidewall. The operating device has a screw coupling rod having an elongated pipe shape, a body having a first side coupled to the screw coupling rod, a rotating member having a first end coupled to a second side of the body in such a manner that a second end of the rotating member rotates about the first end thereof, and a rod receiver coupled to the second end of the rotating member. Due to the support unit, the rod is prevented from being easily separated from the pedicle screw, thereby facilitating minimum incision surgery. The operating device for the pedicle screw allows an operator to easily perform minimum incision surgery while making several incisions for the pedicle screws and the rod in the back of the patient and keeping the size of incisions quite a small.
摘要翻译：公开了一种脊柱固定装置，更具体地，植入脊柱的椎弓根螺钉和用于能够容易地将杆插入椎弓根螺钉的头部的椎弓根螺钉的操作装置，以便牢固地固定脊柱。椎弓根螺钉具有头部，头部包括由第一和第二侧壁限定的凹部，螺钉部和形成在头部的凹部的上部的支撑单元，同时将第一侧壁连接到第二侧壁。该操作装置具有一个具有细长管状形状的螺旋联接杆，一个本体具有一个联接到螺杆联接杆上的第一侧，旋转构件具有一个第一端，该第一端与主体的第二侧连接，旋转构件绕其第一端旋转，并且杆接收器联接到旋转构件的第二端。由于支撑单元，防止杆容易地从椎弓根螺钉分离，从而便于最小切口手术。用于椎弓根螺钉的操作装置允许操作者容易地执行最小切口手术，同时对患者的椎弓根螺钉和杆进行若干切口并且保持切口的尺寸相当小。

72. 发明授权

US07332973B2 Circuit and method for digital phase-frequency error detection 失效
标题翻译：数字相位频率误差检测电路及方法
公开(公告)号：US07332973B2
公开(公告)日：2008-02-19
申请号：US11265442
申请日：2005-11-02
申请人： Hoon Lee , Tirdad Sowlati
发明人： Hoon Lee , Tirdad Sowlati
IPC分类号： H03L7/089 , H03L7/097
CPC分类号： G04F10/005 , H03L7/085 , H03L7/091
摘要： A time-to-digital converter comprises a ring oscillator, a counter, an encoder, and a multi-bit latch. The ring oscillator comprises a first input and a clock input, as well as, a first output responsive to a single cycle of the ring oscillator and a second output responsive to a signal applied at the first input. A counter coupled to the first output generates a first binary word. An encoder coupled to the second output generates a second binary word. The multi-bit latch receives the first and second binary words and generates a composite representation of a phase-frequency error signal. The time-to-digital converter is well suited for digital phase-locked loops used in communications applications and digital phase-locked loops in electromechanical control systems that require high-precision phase-frequency error detection.
摘要翻译：时间 - 数字转换器包括环形振荡器，计数器，编码器和多位锁存器。环形振荡器包括第一输入和时钟输入，以及响应于环形振荡器的单个周期的第一输出和响应于在第一输入处施加的信号的第二输出。耦合到第一输出的计数器产生第一个二进制字。耦合到第二输出的编码器产生第二二进制字。多位锁存器接收第一和第二二进制字，并产生相位 - 频率误差信号的复合表示。时间到数字转换器非常适用于需要高精度相位频率误差检测的机电控制系统中通信应用和数字锁相环中使用的数字锁相环。

73. 发明申请

US20070133549A1 Apparatus and method for managing traffic using VID in EPON 失效
标题翻译： EPON中使用VID管理流量的装置和方法
公开(公告)号：US20070133549A1
公开(公告)日：2007-06-14
申请号：US11635774
申请日：2006-12-07
申请人： Hoon Lee , Tae Yoo , Jung Kim , Yool Kwon , Bong Kim
发明人： Hoon Lee , Tae Yoo , Jung Kim , Yool Kwon , Bong Kim
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L12/4645 , H04L12/66 , H04L47/20 , H04L61/103 , H04L61/6022
摘要： An apparatus and method for managing traffic using a VID in EPON are provided. The apparatus includes a MAC lookup table, a service classification policy table, a service control policy table, a MAC lookup unit, a first and second classification module, a VID learning unit and a first and second service control module. The apparatus classifies all packets of up/downlink transmission flow using a VID into a VID unit, through the first and second classification modules and manages traffic thereof according to the parameters thereof through the first and second service control modules. Accordingly, a large amount of traffic for numerous subscribers and services thereof, which was cannot be processed by the limitation on embodying a typical switch or router, can be processed according to the present invention.
摘要翻译：提供了一种用于使用EPON中的VID来管理业务的装置和方法。该装置包括MAC查找表，服务分类策略表，服务控制策略表，MAC查找单元，第一和第二分类模块，VID学习单元和第一和第二服务控制模块。该装置通过第一和第二分类模块，使用VID将上行/下行链路传输流的所有数据包分类为VID单元，并通过第一和第二服务控制模块根据其参数来管理其流量。因此，根据本发明，可以处理不能通过实施典型交换机或路由器的限制来处理大量用户和其服务的大量业务。

74. 发明申请

US20070109892A1 Memory device and method of operating the same 失效
标题翻译：存储器件及其操作方法
公开(公告)号：US20070109892A1
公开(公告)日：2007-05-17
申请号：US11600552
申请日：2006-11-16
申请人： Hoon Lee , Kee-Won Kwon
发明人： Hoon Lee , Kee-Won Kwon
IPC分类号： G11C7/02
CPC分类号： G11C11/4096 , G11C7/065 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C11/4091 , G11C2207/002 , G11C2207/065
摘要： A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the global input/output line pair. The detect control signal generating unit disables an operation of the sense amplifier and precharges the global input/output line pair to a predetermined voltage. A precharge operation of a memory device may be performed at a higher speed so that a high speed operation of the memory device may be achieved. In addition, the operating time of the sense amplifier may be decreased so that the power consumption of the memory device may be reduced.
摘要翻译：存储器件具有配置用于数据传输的全局输入/输出线对。存储装置包括读出放大器，检测单元和检测控制信号生成单元。读出放大器耦合到全局输入/输出线对。检测单元检测全局输入/输出线对之间的电位差。检测控制信号产生单元禁止读出放大器的操作，并将全局输入/输出线对预充电到预定电压。可以以更高的速度执行存储器件的预充电操作，从而可以实现存储器件的高速操作。此外，可以减小读出放大器的工作时间，从而可以降低存储器件的功耗。

75. 发明申请

US20070096836A1 Circuit and method for digital phase-frequency error detection 失效
标题翻译：数字相位频率误差检测电路及方法
公开(公告)号：US20070096836A1
公开(公告)日：2007-05-03
申请号：US11265442
申请日：2005-11-02
申请人： Hoon Lee , Tirdad Sowlati
发明人： Hoon Lee , Tirdad Sowlati
IPC分类号： H03K3/03
CPC分类号： G04F10/005 , H03L7/085 , H03L7/091
摘要： A time-to-digital converter comprises a ring oscillator, a counter, an encoder, and a multi-bit latch. The ring oscillator comprises a first input and a clock input, as well as, a first output responsive to a single cycle of the ring oscillator and a second output responsive to a signal applied at the first input. A counter coupled to the first output generates a first binary word. An encoder coupled to the second output generates a second binary word. The multi-bit latch receives the first and second binary words and generates a composite representation of a phase-frequency error signal. The time-to-digital converter is well suited for digital phase-locked loops used in communications applications and digital phase-locked loops in electromechanical control systems that require high-precision phase-frequency error detection.
摘要翻译：时间 - 数字转换器包括环形振荡器，计数器，编码器和多位锁存器。环形振荡器包括第一输入和时钟输入，以及响应于环形振荡器的单个周期的第一输出和响应于在第一输入处施加的信号的第二输出。耦合到第一输出的计数器产生第一个二进制字。耦合到第二输出的编码器产生第二二进制字。多位锁存器接收第一和第二二进制字，并产生相位 - 频率误差信号的复合表示。时间到数字转换器非常适用于需要高精度相位频率误差检测的机电控制系统中通信应用和数字锁相环中使用的数字锁相环。

76. 发明申请

US20060247631A1 Spinal pedicle screw assembly 审中-公开
标题翻译：脊柱椎弓根螺钉总成
公开(公告)号：US20060247631A1
公开(公告)日：2006-11-02
申请号：US11254055
申请日：2005-10-19
申请人： Sae Ahn , Jae Lim , Jong Choi , Hoon Lee , Chang Lim , Seo Kim , Se Kim , Hoon Kim
发明人： Sae Ahn , Jae Lim , Jong Choi , Hoon Lee , Chang Lim , Seo Kim , Se Kim , Hoon Kim
IPC分类号： A61F2/30
CPC分类号： A61B17/7037 , A61B17/7032
摘要： Disclosed is a spinal pedicle screw assembly including a spinal pedicle screw cooperating with a spine rod for fixing a spine, which includes: a head-coupling element having an upper and a lower end, a rod-receiving channel opening toward the upper end for receiving the spine rod, female screw threads formed on the inside of the rod-receiving channel, and a connecting bore of a given size extending through the lower end, the connecting bore having an upper end toward the rod-receiving channel and an opposite lower end; a screw rod having an upper and a lower end, a spherical head integrally formed with the upper end thereof for being inserted into the connection bore, and male screw threads formed on the periphery of the screw rod between the spherical head and lower end thereof, the screw rod being fixedly inserted into the pedicle by means of the male screw threads thereof; a tightening screw having a periphery formed with male screw threads for engaging the female screw threads of the rod-receiving channel so as to fix the spine rod in the head-coupling element; and a final fixing screw threadedly engaged by the connecting bore for preventing the spherical head from disconnecting from the head-coupling element.
摘要翻译：公开了一种脊椎椎弓根螺钉组件，其包括与用于固定脊柱的脊柱配合的脊椎椎弓根螺钉，其包括：具有上端和下端的头部联接元件，朝向上端开口的杆接收通道，用于接收脊杆，形成在杆接收通道的内侧的内螺纹螺纹，以及延伸穿过下端的给定尺寸的连接孔，连接孔具有朝向杆接收通道的上端和相对的下端 ; 具有上端和下端的螺杆，与其上端一体形成的用于插入连接孔的球形头，以及形成在螺杆的周边上的球形头部和下端之间的外螺纹，螺杆通过其外螺纹固定插入椎弓根内; 紧固螺钉具有形成有外螺纹的周边，用于接合杆接收通道的内螺纹，以将脊杆固定在头联接元件中; 以及由连接孔螺纹接合的最终固定螺钉，用于防止球头与头部联接元件断开。

77. 发明申请

US20050149821A1 Apparatus for FEC supporting transmission of variable-length frames in TDMA system and method of using the same 失效
标题翻译：用于支持TDMA系统中可变长度帧的传输的FEC的装置及其使用方法
公开(公告)号：US20050149821A1
公开(公告)日：2005-07-07
申请号：US11004401
申请日：2004-12-03
申请人： Hoon Lee , Tae Yoo , Hyeong Lee
发明人： Hoon Lee , Tae Yoo , Hyeong Lee
IPC分类号： G06F11/00 , H03M13/00 , H03M13/25
CPC分类号： H03M13/251 , H03M13/1515 , H03M13/25 , H04L1/0041 , H04L1/0057 , H04L1/0084
摘要： An apparatus for transmitting a FEC frame is provided. The apparatus includes: a selector determining whether to perform FEC encoding on data to be transmitted; a Reed-Solomon encoding assembler receiving the data on which FEC encoding is to be performed as determined by the selector, and dividing the data into k-byte message blocks (k is a positive integer) for output; a Reed-Solomon encoder receiving the message blocks and performing Reed-Solomon encoding on the message blocks; and an output controller receiving an input parity generated by the Reed-Solomon encoding, and outputting the message block and the parity sequentially or outputting the data on which FEC encoding is not to be performed as determined by the selector. In order to correct an error caused by a transmission medium using FEC in a Reed-Solomon code type, FEC encoding/decoding of a frame is performed. A total transmission delay time is not influenced when FEC is bypassed, a delay caused by a shortened codeword is minimized, and a FEC encoding/decoding delays for frames having different lengths are equalized.
摘要翻译：提供了一种用于发送FEC帧的装置。该装置包括：选择器，确定是否对要发送的数据执行FEC编码; 接收由选择器确定的要进行FEC编码的数据的里德 - 所罗门编码汇编器，并将数据划分为k字节消息块（k为正整数）以供输出; 接收消息块的Reed-Solomon编码器，并对消息块执行Reed-Solomon编码; 以及输出控制器，接收由Reed-Solomon编码产生的输入奇偶校验，并顺序输出消息块和奇偶校验，或者输出由选择器确定的不进行FEC编码的数据。为了校正利用Reed-Solomon码类型的使用FEC的传输介质引起的错误，执行帧的FEC编码/解码。当FEC被旁路时，总传输延迟时间不受影响，由缩短的码字引起的延迟最小化，并且对具有不同长度的帧进行FEC编码/解码延迟相等。

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