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71. 发明授权

US07750670B2 System and method for dynamically executing a function in a programmable logic array 失效
标题翻译：用于在可编程逻辑阵列中动态执行功能的系统和方法
公开(公告)号：US07750670B2
公开(公告)日：2010-07-06
申请号：US12185467
申请日：2008-08-04
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17756 , H03K19/1776
摘要： A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between the first and second storage regions. When the function is parsed into a plurality of functional blocks, this configuration allows the RLA to process the function by sequentially processing the functional blocks in alternating directions within the RLA, using the plurality of programmable logic elements to sequentially process each of the functional blocks and using the first and second storage regions to temporarily hold the input and output for that one of the functional blocks.
摘要翻译：具有逻辑容量并被配置为处理具有超过RLA的逻辑容量的总逻辑要求的功能的可重构逻辑阵列（RLA）。 RLA包括第一和第二存储区域以及位于第一和第二存储区域之间的多个可编程逻辑元件。当功能被解析成多个功能块时，该配置允许RLA通过在RLA内沿交替方向依次处理功能块来处理功能，使用多个可编程逻辑元件来顺序地处理每个功能块和使用第一和第二存储区域临时保持该功能块的输入和输出。

72. 发明授权

US07732949B2 System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly 有权
标题翻译：用于在间歇电力环境中预测电力事件的方法的系统，并相应地调度集成电路的计算操作
公开(公告)号：US07732949B2
公开(公告)日：2010-06-08
申请号：US11550573
申请日：2006-10-18
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G05F3/06 , G06F1/00
CPC分类号： C09K11/77 , G06F1/3203
摘要： A system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.
摘要翻译：一种在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的系统和方法。功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路。一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

73. 发明申请

US20090132732A1 UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路SOC环境通用外围处理器系统
公开(公告)号：US20090132732A1
公开(公告)日：2009-05-21
申请号：US11942000
申请日：2007-11-19
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
IPC分类号： G06F3/00
CPC分类号： G06F13/4027
摘要： A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors.
摘要翻译：集成电路（IC）上的通用外围处理器架构包括耦合到接口逻辑器件的第一和第二数据总线，用于实现第一和第二数据总线之间的通信，包括多个信令协议的启用接口。一个或多个处理器与第一和第二数据总线通信以管理IC上的控制功能。数据路径能够在第一和第二数据总线之间传送数据，并与数据存储设备进行通信。数据控制路径实现数据存储设备和处理器之间的通信。

74. 发明申请

US20090125744A1 Structure for a System and Method of Predicting Power Events in an Intermittent Power Environment and Dispatching Computational Operations of an Integrated Circuit Accordingly 有权
标题翻译：一种系统的结构和预测间歇电力环境中的电力事件的方法和集成电路的调度运算
公开(公告)号：US20090125744A1
公开(公告)日：2009-05-14
申请号：US11938899
申请日：2007-11-13
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.
摘要翻译：一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路。一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

75. 发明申请

US20090024862A1 STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS 有权
标题翻译：优化低功率环境下计算效率的结构与方法
公开(公告)号：US20090024862A1
公开(公告)日：2009-01-22
申请号：US11779432
申请日：2007-07-18
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith Williams , Charles S. Woodruff
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith Williams , Charles S. Woodruff
IPC分类号： G06F1/30
CPC分类号： G06F1/3203
摘要： A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source.
摘要翻译：一种在低功耗环境下优化计算效率的方法和结构。该方法包括确定用于在低功率环境中最大化计算效率的最佳点，以及根据所确定的最佳点选择性地控制多个处理单元中的至少一个处理单元的操作。该结构包括多个处理单元，控制多个处理单元中的至少一个处理单元的选择性并行操作的负载管理器和未调节的电源。

76. 发明申请

US20080215923A1 DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TRIGGER) 失效
标题翻译：基于任务调度器的设计结构（交易活动 - 手动触发）
公开(公告)号：US20080215923A1
公开(公告)日：2008-09-04
申请号：US12050982
申请日：2008-03-19
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Charles S. Woodruff
IPC分类号： G06F11/30
CPC分类号： G06F17/5022 , G06F2217/14
摘要： Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.
摘要翻译：公开了用于基于任务的调试器（事务 - 事件 - 作业触发）的装置的设计结构。更具体地，SOC的集成事件监视器包括各自具有功能调试逻辑元件的功能核心。核心连接到链接功能调试逻辑元件的互连结构。每个功能调试逻辑元件专门用于其相应核心的功能，其中功能调试逻辑元件产生功能特定系统事件表。系统事件相对于相关联的核心是特定于功能的，其中系统事件包括交易事件，控制器事件，处理器事件，互连结构仲裁器事件，互连接口核心事件，高速串行链路核心事件和/或编解码器事件。

77. 发明申请

US20080212977A1 FIBER OPTIC TRANSMISSION LINES ON AN SOC 审中-公开
标题翻译：光纤光纤传输线
公开(公告)号：US20080212977A1
公开(公告)日：2008-09-04
申请号：US11772378
申请日：2007-07-02
申请人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
发明人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： H04B10/00
CPC分类号： G02B6/43
摘要： An optical transmission method. Signal transmissions between cores of an integrated circuit are performed. Each signal transmission is between two cores of a different pair of cores of the integrated circuit. Each signal transmission includes transmission of an optical signal in the visible or infrared portion of the electromagnetic spectrum at a wavelength that is specific to each different pair of cores and is a different wavelength for each different pair of cores. There is no overhead for decoding or arbitration in preforming the signal transmissions that would otherwise exist if a same wavelength for the optical signals were permitted for pairs of cores of the different pairs of cores.
摘要翻译：光传输方法。执行集成电路的核心之间的信号传输。每个信号传输在集成电路的不同核心的两个核之间。每个信号传输包括以对于每个不同的核对特定的波长的电磁光谱的可见光或红外部分中的光信号的传输，并且对于每个不同的一对核心是不同的波长。如果对于不同核心对的核对允许相同的光信号波长，则在进行信号传输时，没有解码或仲裁的开销。

78. 发明授权

US07107469B2 Power down processing islands 失效
标题翻译：关闭加工岛屿
公开(公告)号：US07107469B2
公开(公告)日：2006-09-12
申请号：US10604328
申请日：2003-07-11
申请人： Rafael Blanco , John M. Cohn , Kenneth J. Goodnow , Douglas W. Stout , Sebastian T. Ventrone
发明人： Rafael Blanco , John M. Cohn , Kenneth J. Goodnow , Douglas W. Stout , Sebastian T. Ventrone
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y02D10/171
摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.
摘要翻译：一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。输出岛适于由第二规定电压供电。处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

79. 发明授权

US06825711B2 Power reduction by stage in integrated circuit 有权
标题翻译：集成电路中的功耗降低
公开(公告)号：US06825711B2
公开(公告)日：2004-11-30
申请号：US10249684
申请日：2003-04-30
申请人： John M. Cohn , Kenneth J. Goodnow , Scott W. Gould , Douglas W. Stout , Sebastian T. Ventrone
发明人： John M. Cohn , Kenneth J. Goodnow , Scott W. Gould , Douglas W. Stout , Sebastian T. Ventrone
IPC分类号： G05F110
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要翻译：一种集成电路，方法和系统，提供更精细的粒度动态电压控制，无需性能损失。本发明提供了用于在特定周期中动态地改变关键路径上的至少一个级的电压电平的装置。以这种方式，可以为给定期望的阶段提供最佳电压。

80. 发明授权

US06275968B1 Apparatus and method to reduce node toggling in semiconductor devices 失效
标题翻译：减少半导体器件中的节点切换的装置和方法
公开(公告)号：US06275968B1
公开(公告)日：2001-08-14
申请号：US09129921
申请日：1998-08-06
申请人： Alvar A. Dean , Kenneth J. Goodnow , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F1/32 , G06F1/04 , G06F17/505
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded toggling that commonly occurs in many types of logic circuits. The preferred embodiment reduces unneeded node toggling in a circuit by holding a portion of the device at the previous output until the all the inputs have stabilized to their final value during each clock cycle. This reduces power consumption in the device that would normally occur due to unnecessary node toggling.
摘要翻译：根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。优选实施例减少了通常在许多类型的逻辑电路中发生的不必要的切换。优选实施例通过将设备的一部分保持在先前输出来减少电路中的不需要的节点切换，直到所有输入在每个时钟周期内稳定到其最终值。这减少了由于不必要的节点切换而通常发生的设备中的功耗。

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