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71. 发明申请

US20080089106A1 Memory circuit and semiconductor device 失效
标题翻译：存储电路和半导体器件
公开(公告)号：US20080089106A1
公开(公告)日：2008-04-17
申请号：US11907208
申请日：2007-10-10
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C5/06
CPC分类号： G11C7/106 , G11C7/1048 , G11C7/1051 , G11C7/18 , G11C11/4093 , G11C11/4097
摘要： A semiconductor circuit of the invention comprises: a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers each for amplifying data of the memory cell connected to a selected word line through the bit line; a plurality of data holding circuits each for holding data transferred from the plurality of sense amplifiers; and a plurality of selectors each for selecting a data holding circuit from a unit group including a predetermined number of the data holding circuits based on logic input data, and for externally connecting one end of the selected data holding circuit.
摘要翻译：本发明的半导体电路包括：存储单元阵列，包括形成在多个字线和多个位线之间的交叉处的多个存储单元; 多个读出放大器，每个用于放大通过位线连接到所选字线的存储单元的数据; 多个数据保持电路，用于保持从多个读出放大器传送的数据; 以及多个选择器，每个选择器用于从包括基于逻辑输入数据的预定数量的数据保持电路的单元组中选择数据保持电路，以及用于外部连接所选数据保持电路的一端。

72. 发明申请

US20080068909A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080068909A1
公开(公告)日：2008-03-20
申请号：US11902006
申请日：2007-09-18
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4097 , G11C7/1075 , G11C7/18 , G11C8/06 , G11C11/4093 , G11C2207/002 , G11C2207/108
摘要： A semiconductor device of the invention comprises: a memory cell array including memory cells formed at intersections between word lines and bit lines; first and second input/output ports each defined for inputting/outputting data of the memory cell array; sense amplifiers for amplifying data of the memory cells through the bit lines; a first select circuit which is controlled to be on/off by first select control lines extending in an intersecting direction to bit lines and is connected between the sense amplifiers and the first input/output port; a second select circuit which is controlled to be on/off by second select control lines extending along the bit lines and is connected between the sense amplifiers and the second input/output port; and first and second column decoders for selectively activating the first and second select control lines in response to an input column address.
摘要翻译：本发明的半导体器件包括：存储单元阵列，包括在字线和位线之间的交叉处形成的存储单元; 每个被定义用于输入/输出存储单元阵列的数据的第一和第二输入/输出端口; 读出放大器，用于通过位线放大存储器单元的数据; 第一选择电路，被控制为通过在与位线交叉的方向上延伸的第一选择控制线进行开/关，并连接在感测放大器和第一输入/输出端口之间; 第二选择电路，其被控制为沿着位线延伸的第二选择控制线开/关，并连接在读出放大器和第二输入/输出端口之间; 以及第一和第二列解码器，用于响应于输入列地址选择性地激活第一和第二选择控制线。

73. 发明授权

US07317649B2 Semiconductor storage device 有权
公开(公告)号：US07317649B2
公开(公告)日：2008-01-08
申请号：US11393666
申请日：2006-03-31
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C11/4097 , G11C11/4094 , G11C2207/005
摘要： A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense amplifiers on an other side of the bit lines; first switch means which switches a connection state between the one side of the bit lines and the first row of sense amplifiers; second switch means which switches a connection state between the other side of the bit lines and the second row of sense amplifiers; third switch means arranged in the approximate center of the bit lines in an extending direction thereof to switch a connection state of the bit lines; and refresh control means which divides the unit block into two areas and controls the refresh operation using the switch means and the row of sense amplifiers according to which area a selected word line to be refreshed is in.

74. 发明申请

US20080002488A1 SEMICONDUCTOR DEVICE AND MEMORY CIRCUIT INCLUDING A REDUNDANCY ARRANGEMENT 有权
标题翻译：半导体器件和存储器电路，包括冗余布置
公开(公告)号：US20080002488A1
公开(公告)日：2008-01-03
申请号：US11844840
申请日：2007-08-24
申请人： Masatoshi HASEGAWA , Kazuhiko Kajigaya
发明人： Masatoshi HASEGAWA , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C29/808 , G11C7/18 , G11C11/4097 , G11C29/02 , G11C29/025 , G11C29/72 , G11C29/80 , G11C29/848
摘要： In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.
摘要翻译：在位线方向上，多个存储器阵列被布置成包括分别耦合到位线和字线的多个存储器单元，并且读出放大器阵列被布置成包括多个锁存电路，其中输入/输出节点连接到一半的位线对分别提供给放置在位线方向上的存储器垫之间的区域中的存储器堆，从而可以基于每个位替换冗余位线对和相应的冗余读出放大器线对和读出放大器，从而实现有效和合理的Y系统释放。

75. 发明申请

US20070297257A1 Semiconductor memory device capable of canceling out noise development 审中-公开
标题翻译：能够消除噪声发展的半导体存储器件
公开(公告)号：US20070297257A1
公开(公告)日：2007-12-27
申请号：US11889902
申请日：2007-08-17
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.
摘要翻译：动态RAM包含多个动态存储单元，每个动态存储单元包括具有作为选择端子的栅极集合的MOSFET，作为输入/输出端子的一个源极和漏极组，以及连接到电容器的存储节点的另一个源极和漏极以及电容器，分别连接到多个动态存储单元的选择端子的多个字线，分别连接到多个动态存储单元的输入/输出端子的多个互补位线对，以及读出放大器阵列包括多个锁存电路，其分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。电源线以网格形式提供，包括字驱动器上方的一部分。

76. 发明授权

US07310256B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07310256B2
公开(公告)日：2007-12-18
申请号：US11134476
申请日：2005-05-23
申请人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C5/08 , G11C11/12 , G11C11/24
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译：提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。当访问存储器单元时，两个晶体管被激活并且读取该信息。当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

77. 发明授权

US07298662B2 Semiconductor device with power down arrangement for reduce power consumption 有权
标题翻译：具有掉电布置的半导体器件，以降低功耗
公开(公告)号：US07298662B2
公开(公告)日：2007-11-20
申请号：US11483649
申请日：2006-07-11
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

78. 发明申请

US20070242535A1 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US20070242535A1
公开(公告)日：2007-10-18
申请号：US11714867
申请日：2007-03-07
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C7/10
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括第一存储器阵列，多个第二存储器阵列，第一电压发生器和第一焊盘。半导体芯片被分为第一，第二和第三矩形区域，第三矩形区域布置在第一矩形区域和第二矩形区域之间。第一存储器阵列形成在第一矩形区域中。第二存储器阵列形成在第二矩形区域中。电压发生器和第一接合焊盘布置在第三矩形区域中。第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和第二存储器阵列之间没有布置接合焊盘。

79. 发明授权

US07269087B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07269087B2
公开(公告)日：2007-09-11
申请号：US11151417
申请日：2005-06-14
申请人： Masatoshi Hasegawa , Kazuhiko Kajigaya
发明人： Masatoshi Hasegawa , Kazuhiko Kajigaya
IPC分类号： G11C8/00
CPC分类号： G11C29/808 , G11C7/18 , G11C11/4097 , G11C29/02 , G11C29/025 , G11C29/72 , G11C29/80 , G11C29/848
摘要： In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.
摘要翻译：在位线方向上，多个存储器阵列被布置成包括分别耦合到位线和字线的多个存储器单元，并且读出放大器阵列被布置成包括多个锁存电路，其中输入/输出节点连接到一半的位线对分别提供给放置在位线方向上的存储器垫之间的区域中的存储器堆，从而可以基于每个位替换冗余位线对和相应的冗余读出放大器线对和读出放大器，从而实现有效和合理的Y系统释放。

80. 发明申请

US20070183247A1 Semiconductor device 有权
公开(公告)号：US20070183247A1
公开(公告)日：2007-08-09
申请号：US11727430
申请日：2007-03-27
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C5/14 , G11C8/00 , G11C7/00
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

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