专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20110138342A1 Retargeting for Electrical Yield Enhancement 失效
标题翻译：重新定位电收益增强
公开(公告)号：US20110138342A1
公开(公告)日：2011-06-09
申请号：US12630216
申请日：2009-12-03
申请人： Kanak B. Agarwal
发明人： Kanak B. Agarwal
IPC分类号： G06F17/50 , G21K5/10
CPC分类号： G03F1/36
摘要： A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting.
摘要翻译：提供了用于光刻布局的电屈服增强重定向的机制。对一组目标图案执行光学邻近校正，以便产生一组光学邻近校正掩模形状。针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。确定一组目标图案中的一组形状中的至少一种形状的电屈服敏感度。还基于形状的电屈服敏感度来确定该组形状中的至少一个形状中的每一个的重定向的量和方向。基于重定向的数量和方向，为至少一个形状中的每个形状生成具有重定向边缘的新集合的目标图案。

72. 发明申请

US20100327892A1 Parallel Array Architecture for Constant Current Electro-Migration Stress Testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US20100327892A1
公开(公告)日：2010-12-30
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

73. 发明授权

US07834649B2 Method and apparatus for statistical CMOS device characterization 失效
标题翻译：用于统计CMOS器件表征的方法和装置
公开(公告)号：US07834649B2
公开(公告)日：2010-11-16
申请号：US12779038
申请日：2010-05-12
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/26
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译：使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。然后通过将表示线性关系的线的斜率除以激励电压来导出电容。可以对不同的电子设备进行测试，包括晶体管和互连结构。

74. 发明申请

US20100225348A1 METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION 失效
标题翻译：用于统计CMOS器件特征的方法和装置
公开(公告)号：US20100225348A1
公开(公告)日：2010-09-09
申请号：US12779038
申请日：2010-05-12
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/26
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译：使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。然后通过将表示线性关系的线的斜率除以激励电压来导出电容。可以对不同的电子设备进行测试，包括晶体管和互连结构。

75. 发明授权

US07782076B2 Method and apparatus for statistical CMOS device characterization 失效
公开(公告)号：US07782076B2
公开(公告)日：2010-08-24
申请号：US12141862
申请日：2008-06-18
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

76. 发明授权

US07564259B2 Digital circuit with dynamic power and performance control via per-block selectable operating voltage 失效
标题翻译：具有动态功耗和性能控制的数字电路，通过每块可选工作电压
公开(公告)号：US07564259B2
公开(公告)日：2009-07-21
申请号：US11301728
申请日：2005-12-13
申请人： Kanak B. Agarwal , Damir A. Jamsek , Kevin J. Nowka
发明人： Kanak B. Agarwal , Damir A. Jamsek , Kevin J. Nowka
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0016
摘要： A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation for process variation. A set of processing blocks having a power supply selectable from two different power supply voltage levels is provided. The power level of the overall circuit is set by selecting the power supply voltage for each block to yield a combination of blocks that meets operating requirements. Alternatively, one circuit per pair from a set of pairs of redundant logic blocks supplied by the different power supply voltage levels can be selected to meet the operating requirements. The unselected blocks can be disabled by disabling foot devices or disabling transitions at the inputs to the unselected blocks. Performance measurement and feedback circuits can be included to tune the power consumption and performance level of the circuit to meet an expected level.
摘要翻译：具有通过每块可选工作电压电平的动态功率和性能控制的数字电路允许动态定制工作电源以处理需求和/或对工艺变化的补偿。提供了具有可从两个不同电源电压电平选择的电源的一组处理块。通过选择每个块的电源电压来设置整个电路的功率电平，以产生满足运行要求的块组合。或者，可以选择由不同电源电压电平提供的一组冗余逻辑块中的每对一个电路以满足操作要求。可以通过禁用脚装置或禁用未选择块的输入上的转换来禁用未选择的块。可以包括性能测量和反馈电路来调整电路的功耗和性能水平以达到预期的水平。

77. 发明授权

US08804852B2 High bandwidth decompression of variable length encoded data streams 有权
标题翻译：可变长度编码数据流的高带宽解压缩
公开(公告)号：US08804852B2
公开(公告)日：2014-08-12
申请号：US13555547
申请日：2012-07-23
申请人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
发明人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
IPC分类号： H04B1/66
CPC分类号： H03M7/30
摘要： Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.
摘要翻译：提供用于解码可变长度编码数据流的机制。数据处理系统的解码器接收数据的输入行。输入数据行是可变长度编码数据流的一部分。解码器确定输入数据行的位溢出量到下一个输入数据行。解码器根据确定的位溢出量将对准数据的输入行开始于符号边界。解码器对对齐的输入数据行进行标记，以生成一组令牌。每个令牌对应于对齐的下一个输入数据行中的编码符号。解码器基于该组令牌生成数据的输出字。数据的输出字对应于原始数据集中的数据字。

78. 发明授权

US08627244B2 Frequency domain layout decomposition in double patterning lithography 失效
标题翻译：双图案光刻中的频域布局分解
公开(公告)号：US08627244B2
公开(公告)日：2014-01-07
申请号：US13171513
申请日：2011-06-29
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G06F17/50
CPC分类号： G03F7/70466
摘要： A mechanism is provided for frequency domain layout decomposition in double pattern lithography (DPL) based on Fourier coefficient optimization (FCO). The Fourier transform of a layout represents the spatial frequency terms present in the layout. The mechanism models decomposed patterns for two exposures as a function of the corresponding Fourier coefficients. For each exposure, the mechanism sets the corresponding Fourier coefficients to zero for spatial frequency terms greater than the cut-off frequency of the optical system. The mechanism then optimizes non-zero Fourier coefficients for the two exposures to decompose the original target. The mechanism provides frequency domain optimization instead of conventional spatial domain methods, which naturally leads to optics-aware decomposition and stitch insertion in arbitrary two dimensional patterns.
摘要翻译：基于傅里叶系数优化（FCO）的双模式光刻（DPL）中的频域布局分解提供了一种机制。布局的傅里叶变换表示布局中存在的空间频率项。机制模型将两次曝光的分解模式作为相应的傅里叶系数的函数。对于每次曝光，机构将相应的傅立叶系数设置为零，以使空间频率项大于光学系统的截止频率。然后，该机制优化用于两次曝光的非零傅立叶系数以分解原始目标。该机制提供频域优化，而不是传统的空间域方法，这自然导致光学感知分解和针脚插入任意二维模式。

79. 发明申请

US20130007674A1 RESOLVING DOUBLE PATTERNING CONFLICTS 有权
标题翻译：解决双重文字冲突
公开(公告)号：US20130007674A1
公开(公告)日：2013-01-03
申请号：US13171530
申请日：2011-06-29
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A mechanism is provided for resolving patterning conflicts. The mechanism performs decomposition with stitches at all candidate locations to find the solution with the minimum number of conflicts. The mechanism then defines interactions between a layout of a first mask and a layout of a second mask through design rules, as well as interactions of mask1/mask2 with top and bottom layers (i.e., contacts, vial, etc.). The mechanism then gives the decomposed layout and design rule definition to any existing design rule fixing or layout compaction tool to solve native conflicts. The modified design rules are that same-layer spacing equals spacing of single patterning, different-layer spacing equals spacing of final layout, and layer overlap equals minimum overlap length.
摘要翻译：提供了解决图案化冲突的机制。该机制用所有候选位置的针迹进行分解，以最小冲突次数找到解决方案。该机制然后通过设计规则定义第一掩模的布局和第二掩模的布局之间的相互作用，以及mask1 / mask2与顶层和底层（即，触点，小瓶等）的相互作用。然后，该机制将分解的布局和设计规则定义提供给任何现有的设计规则修复或布局压缩工具来解决本机冲突。修改的设计规则是同层间距等于单一图案的间距，不同层间距等于最终布局的间距，层重叠等于最小重叠长度。

80. 发明申请

US20100257493A1 EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS 有权
标题翻译：基于同期长度和移动性分析的有效门限长度电路建模
公开(公告)号：US20100257493A1
公开(公告)日：2010-10-07
申请号：US12416222
申请日：2009-04-01
申请人： Kanak B. Agarwal , Vivek Joshi
发明人： Kanak B. Agarwal , Vivek Joshi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.
摘要翻译：公开了一种用于确定金属氧化物半导体（MOS）门功能限制的计算机实现方法和计算机程序产品。模拟器获得MOS门的多个片，每个片包括至少一个参数，该参数包括片栅宽度和片栅长度。模拟器基于切片的切片门限长度确定每个切片的电流，以形成每个切片的基于长度的电流。模拟器通过对每个切片的基于长度的电流求和来确定MOS栅极的基于长度的电流。模拟器计算每个切片的应力分布。模拟器基于每个切片的应力分布来确定每个切片的切片载波移动性。模拟器基于每个切片载波移动性确定每个切片的基于载波移动性的电流。模拟器基于每个切片的基于载波移动性的电流来确定MOS栅极的载流子迁移率。模拟器基于长度电流确定MOS栅极的有效长度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式