专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07184291B2 Semiconductor memory having charge trapping memory cells and fabrication method 有权
标题翻译：具有电荷捕获存储单元的半导体存储器和制造方法
公开(公告)号：US07184291B2
公开(公告)日：2007-02-27
申请号：US11145541
申请日：2005-06-03
申请人： Michael Bollu , Armin Kohlhase , Christoph Ludwig , Herbert Palm , Josef Willer
发明人： Michael Bollu , Armin Kohlhase , Christoph Ludwig , Herbert Palm , Josef Willer
IPC分类号： G11C5/06
CPC分类号： H01L27/11568 , H01L27/115
摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.
摘要翻译：在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

72. 发明申请

US20070042553A1 Fabrication method for semiconductor memory components 审中-公开
标题翻译：半导体存储器部件的制造方法
公开(公告)号：US20070042553A1
公开(公告)日：2007-02-22
申请号：US11506159
申请日：2006-08-17
申请人： Karl-Heinz Kuesters , Stephan Riedel , Josef Willer
发明人： Karl-Heinz Kuesters , Stephan Riedel , Josef Willer
IPC分类号： H01L21/8236
CPC分类号： H01L27/115 , H01L27/11568
摘要： A storage layer sequence (20) and gate electrodes (34) are arranged on a substrate (10). The gate electrodes (34) may be fabricated in a gate electrode layer (22) made of electrically conductively doped polysilicon. Apart from an optional barrier layer (45), the word lines are solely formed from a material having a low resistivity, preferably from a metal layer (46). Word line spacers (52) are arranged on sidewalls for the purpose of electrical insulation and as a barrier against outdiffusion of metal atoms.
摘要翻译：存储层序列（20）和栅电极（34）布置在基板（10）上。栅极（34）可以制造在由导电掺杂多晶硅制成的栅电极层（22）中。除了可选的阻挡层（45）之外，字线仅由具有低电阻率的材料形成，优选地由金属层（46）形成。字线间隔件（52）布置在侧壁上用于电绝缘并且作为防止金属原子扩散的屏障。

73. 发明授权

US07154138B2 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement 失效
标题翻译：晶体管布置，用于操作晶体管布置作为数据存储元件的方法和用于产生晶体管布置的方法
公开(公告)号：US07154138B2
公开(公告)日：2006-12-26
申请号：US10481278
申请日：2002-06-20
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L27/108 , H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11553 , H01L29/66833 , H01L29/7923
摘要： The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region arranged essentially above the latter, and, in between, a channel region, and also a gate region beside the channel region and, in between, an electrically insulating layer sequence, wherein two mutually spatially separate sections of the electrically insulating layer sequence in each case serve for the storage of charge carriers.
摘要翻译：本发明涉及具有衬底和垂直晶体管的晶体管装置，其包括：第一电极区域，基本上在其上方布置的第二电极区域，以及沟道区域之间以及沟道区域旁边的栅极区域，以及之间，电绝缘层序列，其中电绝缘层序列的两个相互空间分离的部分在每种情况下用于存储电荷载体。

74. 发明申请

US20060245233A1 Multi-bit virtual-ground NAND memory device 有权
标题翻译：多位虚拟NAND存储器件
公开(公告)号：US20060245233A1
公开(公告)日：2006-11-02
申请号：US11119376
申请日：2005-04-29
申请人： Thomas Mikolajick , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Josef Willer , Corvin Liaw
IPC分类号： G11C17/00
CPC分类号： G11C16/0483 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.
摘要翻译：一个电荷捕获多位存储单元的阵列被布置在虚拟地NAND架构中。存储器单元被Fowler-Nordheim擦除，将电子隧穿到存储器层中。写入操作通过热空穴注入来实现。写入电压通过位线施加到两个串联的NAND链。要编程的存储器单元侧的后续位线保持浮置电位，而另一侧的位线被设置为禁止电压，该禁止电压被提供以阻止寻址的存储器单元的程序干扰被编程。电荷俘获存储器单元的虚拟NAND架构能够提高存储密度。

75. 发明申请

US20060197141A1 Charge trapping semiconductor memory element with improved trapping dielectric 有权
标题翻译：电荷捕获半导体存储元件具有改进的俘获电介质
公开(公告)号：US20060197141A1
公开(公告)日：2006-09-07
申请号：US11359783
申请日：2006-02-23
申请人： Klaus-Dieter Ufert , Josef Willer
发明人： Klaus-Dieter Ufert , Josef Willer
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/513 , H01L29/792
摘要： A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel region located between the first and second doping regions, a multilayer gate dielectric which is arranged adjacent to the channel region and has a charge trapping memory layer, and a gate terminal provided above the gate dielectric. The charge trapping memory layer includes at least one sequence of adjacent layers, wherein the sequence of adjacent layers comprises an amorphous silicon carbide layer and an amorphous silicon nitride layer.
摘要翻译：可以通过场效应控制的半导体存储元件包括：第一导电类型的半导体衬底;设置在半导体衬底中的第二导电类型的第一掺杂区;第二导电类型的第二掺杂区; 半导体衬底，位于第一和第二掺杂区域之间的沟道区，与沟道区相邻布置并具有电荷俘获存储层的多层栅极电介质和设置在栅极电介质上方的栅极端子。电荷捕获存储层包括至少一个相邻层序列，其中相邻层的序列包括非晶碳化硅层和非晶氮化硅层。

76. 发明申请

US20060192266A1 Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权
标题翻译：具有电荷捕获存储单元的半导体存储器及其制造方法
公开(公告)号：US20060192266A1
公开(公告)日：2006-08-31
申请号：US11067983
申请日：2005-02-28
申请人： Josef Willer , Thomas Mikolajick , Christoph Ludwig , Norbert Schulze , Karl-Heinz Kuesters
发明人： Josef Willer , Thomas Mikolajick , Christoph Ludwig , Norbert Schulze , Karl-Heinz Kuesters
IPC分类号： H01L29/00
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译：一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器基板中的沟槽中。

77. 发明申请

US20060177980A1 Capacitorless 1-transistor DRAM cell and fabrication method 有权
标题翻译：电容式1晶体管DRAM单元及其制造方法
公开(公告)号：US20060177980A1
公开(公告)日：2006-08-10
申请号：US11367731
申请日：2006-03-03
申请人： Josef Willer
发明人： Josef Willer
IPC分类号： H01L21/8242 , H01L21/76
CPC分类号： H01L27/1203 , H01L27/108 , H01L27/10876 , H01L29/7841 , Y10S257/906
摘要： A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical strip of semiconductor material remains along a sidewall of the dielectric material. A lower portion of the semiconductor body adjacent the sidewall of the dielectric material is doped. A gate dielectric layer is formed over the vertical strip of semiconductor material and a gate electrode is arranged in the cutout.
摘要翻译：通过在半导体本体中形成沟槽来制造半导体器件。电介质材料的区域形成在沟槽的至少下部内。掺杂半导体本体的上部。在半导体材料中形成切口，使得半导体材料的垂直条沿着电介质材料的侧壁保留。与电介质材料的侧壁相邻的半导体本体的下部被掺杂。栅电介质层形成在半导体材料的垂直条上，栅电极设置在切口中。

78. 发明申请

US20060168505A1 Integrated memory device and method for operating the same 有权
标题翻译：集成存储器件及其操作方法
公开(公告)号：US20060168505A1
公开(公告)日：2006-07-27
申请号：US11339846
申请日：2006-01-26
申请人： Corvin Liaw , Josef Willer
发明人： Corvin Liaw , Josef Willer
IPC分类号： H04L1/08 , H04L1/22 , H04L1/24
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/0076 , G11C2213/77 , H01L27/101
摘要： A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines. A checking unit determines whether to invert data values to be stored in memory cells coupled to at least a section of respective ones of the first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values in order to reduce the number memory cells programmed in the low-resistance state and the resulting leakage current.
摘要翻译：存储器件包括存储器单元阵列，其包括具有非反应电阻的存储元件，其大小可编程为呈现高电阻状态或低电阻状态。第一和第二行的集合提供对存储器单元的访问，其中每个存储器单元的存储元件耦合在第一行之一和第二行中的一个之间。检查单元基于将以高电阻状态编程的存储器单元的数量或低电阻来确定是否反转要存储在耦合到第一行中的相应的第一行的至少一部分的存储器单元中的数据值作为数据值的结果，为了减少在低电阻状态下编程的存储单元数量和所产生的漏电流。

79. 发明授权

US07034336B2 Capacitorless 1-transistor DRAM cell and fabrication method 失效
标题翻译：电容式1晶体管DRAM单元及其制造方法
公开(公告)号：US07034336B2
公开(公告)日：2006-04-25
申请号：US10911994
申请日：2004-08-05
申请人： Josef Willer
发明人： Josef Willer
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/108 , H01L27/10876 , H01L29/7841 , Y10S257/906
摘要： The channel region (11) and the source-drain regions (9, 10) are arranged vertically at a sidewall of a dielectric trench filling (4). On the opposite side, the semiconductor material is bounded by the gate dielectric (18) and the gate electrode (16), which is arranged in a cutout of the semiconductor material. A memory cell array comprises a multiplicity of vertically oriented strip-type semiconductor regions in which source-drain regions are implanted at the top and bottom and a channel region embedded in insulating material on all sides is present in between as a floating body.
摘要翻译：沟道区域（11）和源极 - 漏极区域（9,10）垂直布置在电介质沟槽填充物（4）的侧壁处。在相反的一侧，半导体材料由布置在半导体材料的切口中的栅极电介质（18）和栅电极（16）所限定。存储单元阵列包括多个垂直取向的带状半导体区域，其中源极 - 漏极区域在顶部和底部被注入，并且在所有侧面上嵌入绝缘材料的沟道区域作为浮体存在于其间。

80. 发明授权

US06972226B2 Charge-trapping memory cell array and method for production 失效
标题翻译：电荷俘获记忆体阵列和生产方法
公开(公告)号：US06972226B2
公开(公告)日：2005-12-06
申请号：US10815223
申请日：2004-03-31
申请人： Joachim Deppe , Josef Willer
发明人： Joachim Deppe , Josef Willer
IPC分类号： H01L21/8246 , H01L27/115 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11568
摘要： In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.
摘要翻译：在包括电荷捕获存储器单元的存储单元阵列中，沿用于将相邻存储器单元的源极/漏极区域连接到位线的字线方向的局部互连通过在上部的半导体材料的侧壁上选择性沉积硅或多晶硅桥来形成浅沟槽隔离物的电介质材料中的凹槽穿过字线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式