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71. 发明申请

US20110095351A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110095351A1
公开(公告)日：2011-04-28
申请号：US12980399
申请日：2010-12-29
申请人： Sang-Hun Jeon , Jung-Dal Choi , Chang-Seok Kang , Won-Seok Jung
发明人： Sang-Hun Jeon , Jung-Dal Choi , Chang-Seok Kang , Won-Seok Jung
IPC分类号： H01L29/788
CPC分类号： H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.
摘要翻译：半导体器件包括在半导体衬底中的器件隔离层，由器件隔离层限定的有源区，包括主表面的有源区和包括低于主表面的底表面的凹陷区，以及栅电极形成在所述凹部区域上，其中，所述器件隔离层的与所述凹部区域相邻的顶面低于所述凹部区域的底面。

72. 发明申请

US20100133604A1 Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices 有权
标题翻译：具有具有不同宽度的导电图案的门结构的半导体器件和制造这种器件的方法
公开(公告)号：US20100133604A1
公开(公告)日：2010-06-03
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

73. 发明申请

US20080093656A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080093656A1
公开(公告)日：2008-04-24
申请号：US11709814
申请日：2007-02-23
申请人： Sang-Hun Jeon , Jung-Dal Choi , Chang-Seok Kang , Won-Seok Jung
发明人： Sang-Hun Jeon , Jung-Dal Choi , Chang-Seok Kang , Won-Seok Jung
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.
摘要翻译：半导体器件包括在半导体衬底中的器件隔离层，由器件隔离层限定的有源区，包括主表面的有源区和包括低于主表面的底表面的凹陷区，以及栅电极形成在所述凹部区域上，其中，所述器件隔离层的与所述凹部区域相邻的顶面低于所述凹部区域的底面。

74. 发明申请

US20070284651A1 Charge-trap type non-volatile memory devices and related methods 有权
标题翻译：充电陷阱型非易失性存储器件及相关方法
公开(公告)号：US20070284651A1
公开(公告)日：2007-12-13
申请号：US11724870
申请日：2007-03-16
申请人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
发明人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. Related structures are also discussed.
摘要翻译：形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。还讨论了相关结构。

75. 发明授权

US08643077B2 Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps 有权
标题翻译：非易失性存储器件包括具有不同能带隙的子层的阻挡绝缘图案
公开(公告)号：US08643077B2
公开(公告)日：2014-02-04
申请号：US13305930
申请日：2011-11-29
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

76. 发明授权

US08314457B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08314457B2
公开(公告)日：2012-11-20
申请号：US13095408
申请日：2011-04-27
申请人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

77. 发明授权

US08089114B2 Non-volatile memory devices including blocking and interface patterns between charge storage patterns and control electrodes and related methods 有权
标题翻译：包括电荷存储模式和控制电极之间的阻塞和接口模式的非易失性存储器件及相关方法
公开(公告)号：US08089114B2
公开(公告)日：2012-01-03
申请号：US12266032
申请日：2008-11-06
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

78. 发明授权

US07973357B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US07973357B2
公开(公告)日：2011-07-05
申请号：US12338308
申请日：2008-12-18
申请人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun-Suk Kim , Sun-Il Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

79. 发明申请

US20100221886A1 Methods of Forming Charge-Trap Type Non-Volatile Memory Devices 有权
标题翻译：形成电荷陷阱型非易失性存储器件的方法
公开(公告)号：US20100221886A1
公开(公告)日：2010-09-02
申请号：US12766272
申请日：2010-04-23
申请人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
发明人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.
摘要翻译：形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。

80. 发明授权

US07732856B2 Charge-trap type non-volatile memory devices and related methods 有权
标题翻译：充电陷阱型非易失性存储器件及相关方法
公开(公告)号：US07732856B2
公开(公告)日：2010-06-08
申请号：US11724870
申请日：2007-03-16
申请人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
发明人： Jae-Sung Sim , Jung-Dal Choi , Chang-Seok Kang
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. Related structures are also discussed.
摘要翻译：形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。还讨论了相关结构。

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