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71. 发明授权

US08278200B2 Metal-semiconductor intermixed regions 有权
标题翻译：金属半导体混合区域
公开(公告)号：US08278200B2
公开(公告)日：2012-10-02
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

72. 发明授权

US06882015B2 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 失效
公开(公告)号：US06882015B2
公开(公告)日：2005-04-19
申请号：US10660755
申请日：2003-09-12
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/02 , H01L27/08 , H01L29/76
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

73. 发明授权

US4495512A Self-aligned bipolar transistor with inverted polycide base contact 失效
标题翻译：自对准双极晶体管与反向多晶硅基极接触
公开(公告)号：US4495512A
公开(公告)日：1985-01-22
申请号：US385740
申请日：1982-06-07
申请人： Randall D. Isaac , Tak H. Ning
发明人： Randall D. Isaac , Tak H. Ning
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L29/10 , H01L23/48 , H01L29/46 , H01L29/72
CPC分类号： H01L29/66272 , H01L21/28518 , H01L29/1004 , Y10S148/035
摘要： An inverted polycide extrinsic base contact serves as a diffusion source, yet still has low resistivity and is readily etchable down to silicon by techniques useful in manufacturing integrated circuits. The extrinsic base contact layer is made up of a metal silicide (e.g. WSi.sub.2) with an overlying doped polysilicon layer with coextensive apertures through doped polysilicon and metal silicide layers defining the emitter and intrinsic base region.The extrinsic base region is formed by diffusing boron impurities from the p.sup.+ polysilicon layer through the silicide layer. The silicide layer is of a metal silicide such as tungsten silicide (WSi.sub.2). The polysilicon layer acts as a diffusion source, since appropriate dopants (e.g., boron) diffuse rapidly through the metal silicide. Both the top surface of the p.sup.+ polysilicon layer and the sidewall edges of the polysilicon and silicide layers are covered by an insulating layer (e.g. SiO.sub.2) which also separates the emitter contact from the base contact layers.
摘要翻译：反向多硅化物非本征基极接触用作扩散源，但仍具有低电阻率，并且通过可用于制造集成电路的技术容易地向硅蚀刻。外部基极接触层由金属硅化物（例如WSi2）与具有共同延伸孔的上覆掺杂多晶硅层组成，掺杂多晶硅和金属硅化物层限定发射极和本征基极区。通过从p +多晶硅层通过硅化物层扩散硼杂质形成非本征基区。硅化物层是诸如硅化钨（WSi2）之类的金属硅化物。多晶硅层充当扩散源，因为合适的掺杂剂（例如硼）迅速扩散通过金属硅化物。 p +多晶硅层的顶表面和多晶硅和硅化物层的侧壁边缘都被绝缘层（例如SiO 2）覆盖，绝缘层也将发射极接触与基极接触层分开。

74. 发明授权

US4338622A Self-aligned semiconductor circuits and process therefor 失效
标题翻译：自对准半导体电路及其工艺
公开(公告)号：US4338622A
公开(公告)日：1982-07-06
申请号：US53473
申请日：1979-06-29
申请人： George C. Feth , Tak H. Ning , Denny D. Tang , Siegfried K. Wiedmann , Hwa N. Yu
发明人： George C. Feth , Tak H. Ning , Denny D. Tang , Siegfried K. Wiedmann , Hwa N. Yu
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L21/60 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/04
CPC分类号： H01L21/76897 , H01L21/28525 , H01L27/0233
摘要： A semiconductor circuit in which a plurality of transistors is provided, the collector regions/contacts and the base regions/contacts of the transistors being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors of these transistors can be butted to a field oxide to reduce the extrinsic base area and to minimize excess charge storage in the base region. The base contacts, whether polysilicon or metal, etc. provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow. The use of a polysilicon layer for the base contacts, where "fingers" are provided by the polysilicon layer, enhances wirability and the mode of fabrication of the structure, since the polysilicon fingers can have an insulating layer (grown oxide) thereover to provide electrical isolation from over-lying conductors. These self-alignment techniques provide enhanced electrical properties since the distance between the base and collector contacts is minimized and since the base-emitter depletion layer capacitance, the stored charge and the base series resistance are reduced. From a processing standpoint, an additional masking step is not required to form the collector regions.
摘要翻译：提供多个晶体管的半导体电路，晶体管的集电极区域/触点和基极区域/触点相互自对准。在一个实施例中，集电器具有导电层接触（例如金属）并且与多晶硅基底触点自对准，而在另一实施例中，基极触点由导电（金属）层组成，而多晶硅用于集电极触点。这些晶体管的集电极可以对接到场氧化物以减少外部基极面积并且使基极区域中的过剩电荷存储最小化。基极触点（无论是多晶硅还是金属）等提供交替的基极电流路径，使得外部基极面积的去除不会不利地影响可流过的基极电流的总量。由于多晶硅指状物可以具有绝缘层（生长的氧化物）以提供电气，所以使用多晶硅层用于基底触点，其中“指状”由多晶硅层提供，从而提高了结构的布线性和制造方式，与绝缘导体隔离。这些自对准技术提供增强的电性能，因为基极和集电极触点之间的距离最小化，并且由于基极 - 发射极耗尽层电容，存储电荷和基极串联电阻减小。从处理的观点来看，不需要附加的掩模步骤来形成收集区域。

75. 发明授权

US4282540A FET Containing stacked gates 失效
标题翻译：包含堆叠栅极的FET
公开(公告)号：US4282540A
公开(公告)日：1981-08-04
申请号：US86608
申请日：1979-10-19
申请人： Tak H. Ning , Carlton M. Osburn , Hwa N. Yu
发明人： Tak H. Ning , Carlton M. Osburn , Hwa N. Yu
IPC分类号： H01L21/033 , H01L21/28 , H01L29/49 , H01L29/788 , H01L29/78
CPC分类号： H01L21/28273 , H01L21/033 , H01L29/4916 , H01L29/7881
摘要： A field effect transistor (FET) comprising a floating gate and a control gate in a stacked relationship with each other and being self-aligned with each other and self-aligned with respect to source and drain regions. The fabrication technique employed comprises delineating both the floating gate and control gate in the same lithographic masking step.
摘要翻译：一种场效应晶体管（FET），其包括彼此堆叠关系的浮置栅极和控制栅极，并且彼此自对准并相对于源极和漏极区域自对准。所采用的制造技术包括在相同的光刻掩模步骤中描绘浮动栅极和控制栅极。

76. 发明授权

US08558210B2 Polysilicon emitter BJT access device for PCRAM 有权
标题翻译：用于PCRAM的多晶硅发射体BJT接入装置
公开(公告)号：US08558210B2
公开(公告)日：2013-10-15
申请号：US13449378
申请日：2012-04-18
申请人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
发明人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/0623 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.
摘要翻译：具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。间隔层包含在绝缘区域内。

77. 发明申请

US20120295439A1 Metal-Semiconductor Intermixed Regions 审中-公开
标题翻译：金属半导体混合区域
公开(公告)号：US20120295439A1
公开(公告)日：2012-11-22
申请号：US13564181
申请日：2012-08-01
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

78. 发明申请

US20120199806A1 POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM 有权
标题翻译：用于PCRAM的多晶硅发射器BJT接入装置
公开(公告)号：US20120199806A1
公开(公告)日：2012-08-09
申请号：US13449378
申请日：2012-04-18
申请人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
发明人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
IPC分类号： H01L47/00
CPC分类号： H01L45/148 , H01L27/0623 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.
摘要翻译：具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。间隔层包含在绝缘区域内。

79. 发明申请

US20120139009A1 SOI SiGe-Base Lateral Bipolar Junction Transistor 有权
标题翻译： SOI SiGe-Base侧向双极结晶体管
公开(公告)号：US20120139009A1
公开(公告)日：2012-06-07
申请号：US12958647
申请日：2010-12-02
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L29/737 , H01L21/8222
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

80. 发明授权

US08120095B2 High-density, trench-based non-volatile random access SONOS memory SOC applications 有权
标题翻译：高密度，基于沟槽的非易失性随机存取SONOS存储器SOC应用
公开(公告)号：US08120095B2
公开(公告)日：2012-02-21
申请号：US11955940
申请日：2007-12-13
申请人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
发明人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , G11C16/0433 , H01L27/11565 , H01L27/1157
摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.
摘要翻译：本发明提供了具有可随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元，以及包括体现在机器可读介质中的半导体存储器件的设计结构。在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于具有1至2μm的沟槽深度的沟槽结构，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

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