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71. 发明授权

US07763518B2 Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof 失效
标题翻译：具有用于低衬底偏置操作的薄埋氧化物（BOX）上的反向集电极的超薄SOI垂直双极晶体管及其方法
公开(公告)号：US07763518B2
公开(公告)日：2010-07-27
申请号：US12099437
申请日：2008-04-08
申请人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L21/331
CPC分类号： H01L29/7317
摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.
摘要翻译：本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

72. 发明申请

US20090184356A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20090184356A1
公开(公告)日：2009-07-23
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

73. 发明申请

US20090173980A1 PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR 有权
标题翻译：提供隔离通过深度电容电容器进行字线传输
公开(公告)号：US20090173980A1
公开(公告)日：2009-07-09
申请号：US11969989
申请日：2008-01-07
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译：存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。衬垫可以是一层氧化物上的氮化物层。一些STI可以覆盖衬垫的一部分。在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。

74. 发明授权

US07485537B2 Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness 失效
标题翻译：制造具有多数载流子积累层的垂直双极晶体管的方法，作为具有降低的掩埋氧化物厚度的SOI BiCMOS的子集电极
公开(公告)号：US07485537B2
公开(公告)日：2009-02-03
申请号：US11490326
申请日：2006-07-20
申请人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/76
CPC分类号： H01L29/7317 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66265
摘要： The present invention provides a a method of fabricating bipolar junction transistors (BJTs) on selected areas of a very thin buried oxide (BOX) using a conventional silicon-on-insulator (SOI) starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.
摘要翻译：本发明提供一种使用具有厚BOX的常规绝缘体上硅（SOI）起始晶片在非常薄的掩埋氧化物（BOX）的选定区域上制造双极结型晶体管（BJT）的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

75. 发明授权

US07276751B2 Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same 有权
标题翻译：与中间线金属触点集成的沟槽金属 - 绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US07276751B2
公开(公告)日：2007-10-02
申请号：US11162413
申请日：2005-09-09
申请人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
发明人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
IPC分类号： H01L29/76
CPC分类号： H01L27/10861 , H01L28/91 , H01L29/945
摘要： The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region. The present invention also relates to a fabrication process, which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material.
摘要翻译：本发明涉及一种半导体器件，其包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选至少一个场效应晶体管（FET）。沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。本发明还涉及一种制造工艺，其将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。

76. 发明授权

US07193262B2 Low-cost deep trench decoupling capacitor device and process of manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

77. 发明授权

US07118986B2 STI formation in semiconductor device including SOI and bulk silicon regions 失效
标题翻译：在包括SOI和体硅区域的半导体器件中形成STI
公开(公告)号：US07118986B2
公开(公告)日：2006-10-10
申请号：US10710060
申请日：2004-06-16
申请人： Michael D. Steigerwalt , Mahender Kumar , Herbert L. Ho , David M. Dobuzinsky , Johnathan E. Faltermeier , Denise Pendleton
发明人： Michael D. Steigerwalt , Mahender Kumar , Herbert L. Ho , David M. Dobuzinsky , Johnathan E. Faltermeier , Denise Pendleton
IPC分类号： H01L21/76
CPC分类号： H01L21/7624 , H01L21/3081 , H01L21/31612 , H01L21/76283
摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.
摘要翻译：公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。可以通过使用STI掩模蚀刻到最上层的硅层，同时在SOI和体硅区域中蚀刻STI，进行蚀刻到体硅区域中期望深度并停止在SOI区域的埋入绝缘体上的定时蚀刻，并蚀刻穿过SOI区域的埋层绝缘体。用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

78. 发明授权

US06670675B2 Deep trench body SOI contacts with epitaxial layer formation 有权
公开(公告)号：US06670675B2
公开(公告)日：2003-12-30
申请号：US09922892
申请日：2001-08-06
申请人： Herbert L. Ho , S. Sundar K. Iyer , Babar A. Khan , Robert Hannon
发明人： Herbert L. Ho , S. Sundar K. Iyer , Babar A. Khan , Robert Hannon
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78612
摘要： A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polysilicon. An electrical device can be formed to overlie the body contact. Thus, no additional circuitry or conductive path is required to electrically connect a body contact and a device region. Also, the body contact provides a predictable electrical characteristics without sacrificing the benefits attained from using the SOI substrate and conservation surface space on the semiconductor die.

79. 发明授权

US06486043B1 Method of forming dislocation filter in merged SOI and non-SOI chips 失效
标题翻译：在合并SOI和非SOI芯片中形成位错滤波器的方法
公开(公告)号：US06486043B1
公开(公告)日：2002-11-26
申请号：US09652711
申请日：2000-08-31
申请人： Robert Hannon , Herbert L. Ho , Subramanian Iyer , S. Sundar Kumar Iyer
发明人： Robert Hannon , Herbert L. Ho , Subramanian Iyer , S. Sundar Kumar Iyer
IPC分类号： H01L2120
CPC分类号： H01L21/76264 , H01L21/76267 , H01L21/76283
摘要： A method for forming a semiconductor devices structure includes providing a semiconductor substrate, forming a deep trench continuously in the substrate to separate a first region from a second region, and then forming a silicon-on-insulator region in the first region while maintaining a non-silicon-on-insulator region in the second region. The deep trench has a depth which is at least as deep as the depth of the buried oxide in the substrate. The invention also includes a device structure resulting from the method.
摘要翻译：一种用于形成半导体器件结构的方法包括提供半导体衬底，在衬底中连续形成深沟槽以将第一区域与第二区域分离，然后在第一区域中形成绝缘体上硅区域，同时保持非 - - 第二区域中的绝缘体上硅区域。深沟槽的深度至少与衬底中的掩埋氧化物的深度一样深。本发明还包括由该方法得到的装置结构。

80. 发明授权

US09059319B2 Embedded dynamic random access memory device and method 有权
标题翻译：嵌入式动态随机存取存储器件及方法
公开(公告)号：US09059319B2
公开(公告)日：2015-06-16
申请号：US12692760
申请日：2010-01-25
申请人： Brent A. Anderson , John E. Barth, Jr. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
发明人： Brent A. Anderson , John E. Barth, Jr. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
IPC分类号： H01L27/108 , H01L21/84 , H01L29/66
CPC分类号： H01L21/84 , H01L27/1087 , H01L27/10894 , H01L29/66181
摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.
摘要翻译：本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法晶圆。本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。

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