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    • 72. 发明申请
    • Apparatus and method for electron beam inspection with projection electron microscopy
    • 用投影电子显微镜进行电子束检查的装置和方法
    • US20070069127A1
    • 2007-03-29
    • US11478615
    • 2006-07-03
    • Hirohito OkudaTakashi HirolHiroshi Makino
    • Hirohito OkudaTakashi HirolHiroshi Makino
    • G21K7/00
    • H01J37/21G01R31/307H01J37/244H01J37/29H01J2237/216H01J2237/2443H01J2237/2446H01J2237/262
    • An apparatus and method for electron beam inspection with projection electron microscopy, is constructed so as to allow correction of changes in focus offsets due to changes in the electrically charged state particularly during inspection. The apparatus includes: a focus measure sensor unit; a focus measure calculation unit which calculates focus measure from the multiple image signals converted by the focus measure sensor unit; a focus position calculation unit which calculates the height of a confocal plane conjugate to the plane of convergence of a planar electron beam by an objective lens, on the basis of the calculated focus measure, and then calculates the focus position of the objective lens on the basis of the calculated height of the confocal plane; and a focus position correction unit which corrects the focus position of the objective lens according to the calculated focus position of the objective lens.
    • 用投影电子显微镜进行电子束检查的装置和方法被构造成允许校正由于带电状态的变化引起的焦点偏移变化,特别是在检查期间。 该装置包括:焦距测量传感器单元; 焦点测量计算单元,其从由所述焦点测量传感器单元转换的多个图像信号计算焦点测量; 焦点位置计算单元,基于计算出的焦点测量,计算由物镜与平面电子束的会聚平面共轭的高度,然后计算物镜的聚焦位置 共焦平面计算高度的基础; 以及聚焦位置校正单元,其根据计算出的物镜的聚焦位置校正物镜的聚焦位置。
    • 74. 发明授权
    • Bi-directional bus circuitry executing bi-directional data transmission while avoiding floating state
    • 双向总线电路执行双向数据传输,同时避免浮动状态
    • US06857039B1
    • 2005-02-15
    • US09615070
    • 2000-07-12
    • Hiroshi Makino
    • Hiroshi Makino
    • G06F3/00G06F13/40G11C7/10
    • G06F13/4077
    • A data bus included in a bi-directional bus circuitry is divided into a first bus node and a second bus node by a repeater circuit. The repeater circuit includes a first tristate buffer for amplifying and transmitting data from the first bus node to the second bus node, and a second tristate buffer connected in reverse direction. When the data bus is not used, the first and second tristate buffers are both activated, and the repeater circuit functions as a latch circuit. Therefore, in the bi-directional bus circuitry, even when the data bus is not used, the potential level of the data bus can be prevented from being left unfixed, ensuring stable operation.
    • 包括在双向总线电路中的数据总线通过中继器电路被分成第一总线节点和第二总线节点。 中继器电路包括用于放大和传输数据从第一总线节点到第二总线节点的第一三态缓冲器,以及反向连接的第二三态缓冲器。 当不使用数据总线时,第一和第二三态缓冲器都被激活,并且中继器电路用作锁存电路。 因此,在双向总线电路中,即使不使用数据总线,也可以防止数据总线的潜在电平不固定,确保稳定运行。
    • 75. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US06556071B2
    • 2003-04-29
    • US10098432
    • 2002-03-18
    • Hiromi NotaniHiroshi Makino
    • Hiromi NotaniHiroshi Makino
    • G05F110
    • H02M3/07H02M2001/0032Y02B70/16
    • On a sleep state, a voltage dropping circuit 2 supplies a power supply line VA1 with a voltage obtained by dropping a voltage of a power supply line VA2, instead of a voltage in accordance with ON state of a switch QA1. A power supply line GND has a voltage equal to the ground voltage. A charge pump circuit 10 outputs the ground voltage on an active state. The charge pump circuit 10 outputs a voltage which is lower than the ground voltage, on the sleep state. A source electrode and a substrate electrode are connected to the power supply lines VA1 and VA2 in each of PMOS transistors Q3 and Q4 of an internal circuit 1 (latch circuit), respectively. A source electrode is connected to the power supply line GND in each of nMOS transistors Q5 and Q6 of the internal circuit 1. A substrate electrode is supplied with the voltage which is outputted from the charge pump circuit, in each of the nMOS transistors Q5 and Q6 of the internal circuit 1. As a result, it is possible to reduce a leakage current withholding data in the internal circuit on the sleep state, even if the supply voltage drops on the sleep state.
    • 在睡眠状态下,电压下降电路2向电源线VA1提供通过降低电源线VA2的电压而获得的电压,而不是根据开关QA1的导通状态的电压。 电源线GND具有等于接地电压的电压。 电荷泵电路10在接通状态下输出接地电压。 电荷泵电路10在睡眠状态下输出低于接地电压的电压。 源电极和基板电极分别连接到内部电路1(锁存电路)的PMOS晶体管Q3和Q4中的电源线VA1和VA2。 源电极连接到内部电路1的nMOS晶体管Q5和Q6中的每一个中的电源线GND。在每个nMOS晶体管Q5中向基板电极提供从电荷泵电路输出的电压, Q6。因此,即使电源电压下降到休眠状态,也可以在睡眠状态下减少内部电路中的泄漏电流保留数据。
    • 76. 发明授权
    • Sliding roof device
    • 滑动屋顶装置
    • US06431644B1
    • 2002-08-13
    • US09697436
    • 2000-10-27
    • Youji NagashimaKenji MaetaHiroshi MakinoTakashi Kitani
    • Youji NagashimaKenji MaetaHiroshi MakinoTakashi Kitani
    • B60J7057
    • B60J7/0573B60J7/022B60J7/057
    • A sliding roof device is made up of a pair of laterally spaced guide rails provided at inner peripheries of an open area formed in a vehicular roof panel, the guide rails supporting a movable panel in movable fashion in order to open and close the open area; a front frame connecting a front end of one of the guide rails and a front end of the other, the front frame and the pair of the guide rails constituting a sunroof frame; and a driving mechanism including a motor, a gear mechanism driven by the motor, an output gear associated with the gear mechanism, a geared cable engaged with the output gear in meshing fashion and connected to the movable panel for the movement thereof when the motor is turned on, and a casing pipe through which the geared cable is passed in movable fashion, characterized in that a housing and a box are provided, the housing placing the output gear outside the sunroof frame, the housing accommodating therein the gear mechanism, the box being formed integrally with the sunroof frame, the box covering the meshing engagement between the geared cable and the output gear.
    • 滑动车顶装置由设置在车顶板的开放区域的内周侧的一对横向间隔开的导轨构成,导轨以可移动的方式支撑可动面板,以打开和关闭开放区域; 连接导轨中的一个的前端和另一个的前端的前框架,前框架和构成天窗框架的一对导轨; 以及包括电动机,由电动机驱动的齿轮机构,与齿轮机构相关联的输出齿轮的驱动机构,以啮合的方式与输出齿轮啮合并连接到可动面板的齿轮传动电缆,用于当马达为 打开,以及可移动方式通过所述齿轮传动电缆的套管,其特征在于,设置有壳体和箱体,所述壳体将所述输出齿轮放置在所述天窗框架外部,所述壳体容纳在所述齿轮机构中,所述箱体 与天窗框架一体形成,该箱体覆盖齿轮传动电缆与输出齿轮之间的啮合。
    • 80. 发明授权
    • Hardware implemented multiplier
    • 硬件实现乘数
    • US5473559A
    • 1995-12-05
    • US168498
    • 1993-12-22
    • Hiroshi Makino
    • Hiroshi Makino
    • G06F7/49G06F7/48G06F7/52G06F7/533H03M7/04
    • H03M7/04G06F7/4824
    • A sign inverting Booth encoder included in an encoding circuit generates a control signal designating a partial product having a sign different from that designated by an output signal generated from a conventional Booth encoder. A partial product generating circuit generates a partial product according to the control signal from the encoding circuit. A partial product having a sign inverted or non-inverted is generated from a shifter/inverter circuit. A converting circuit generates three-value redundant binary numbers using a sign inverted partial product and a sign non-inverted partial product as a set. An intermediate sum generating circuit performs a redundant binary addition of the three-value redundant binary numbers to generate a final redundant binary number. A final adding circuit converts the finally generated three-value redundant binary number into an ordinary binary number to generate a product Z of binary numbers X and Y. As a result, a multiplier performing multiplication at a high speed with a smaller number of elements is implemented.
    • 包括在编码电路中的符号反转布斯编码器产生指定具有与由常规布斯编码器产生的输出信号指定的符号不同的符号的部分乘积的控制信号。 部分乘积生成电路根据来自编码电路的控制信号生成部分乘积。 从移位器/逆变器电路产生具有反转或非反转符号的部分乘积。 A转换电路使用符号反向部分乘积和符号非反相部分乘积作为集合来生成三值冗余二进制数。 中间和产生电路执行三值冗余二进制数的冗余二进制相加以生成最终的冗余二进制数。 最后的加法电路将最终产生的三值冗余二进制数转换为普通二进制数,以生成二进制数X和Y的乘积Z。结果是,以较小数量的元素高速乘法的乘法器是 实施。