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71. 发明授权

US07298011B2 Semiconductor device with recessed L-shaped spacer and method of fabricating the same 有权
标题翻译：具有凹形L形间隔件的半导体器件及其制造方法
公开(公告)号：US07298011B2
公开(公告)日：2007-11-20
申请号：US11215103
申请日：2005-08-30
申请人： Kong-Beng Thei , Chung-Long Cheng , Harry Chuang
发明人： Kong-Beng Thei , Chung-Long Cheng , Harry Chuang
IPC分类号： H01L29/94
CPC分类号： H01L29/6656 , H01L21/28052 , H01L21/76897 , H01L29/66507 , H01L29/6653
摘要： A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.
摘要翻译：具有凹入的L形间隔物的半导体器件及其制造方法。凹进的L形间隔件包括垂直部分和水平部分。垂直部分设置在导体图案的下侧壁上，露出其上侧壁。顶部间隔物在L形间隔件上，其中L形间隔件的垂直部分与顶部间隔物的宽度比为至少约2:1。

72. 发明申请

US20060163734A1 Fuse structure and method for making the same 审中-公开
标题翻译：保险丝结构及制作方法
公开(公告)号：US20060163734A1
公开(公告)日：2006-07-27
申请号：US11041585
申请日：2005-01-24
申请人： Kong-Beng Thei , Chung-Long Cheng , Chung-Shi Liu , Harry Chuang
发明人： Kong-Beng Thei , Chung-Long Cheng , Chung-Shi Liu , Harry Chuang
IPC分类号： H01L23/48
CPC分类号： H01L23/5258 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to form openings, with each opening being aligned with one of the fuse connection or bonding connection features. A conductive layer is formed on the passivation layer and in the openings. The conductive layer is patterned to form bonding features and fuse structures. Each bonding feature is in contact with one of the bonding connection features, and each fuse structure is in contact with two of the fuse connection features. A cap dielectric layer is formed over the fuse structures and patterned to expose at least one of the bonding features while leaving the fuse structures covered.
摘要翻译：提供了一种熔丝结构和用于制造熔丝结构的方法。在一个示例中，该方法包括在半导体衬底上提供多层互连结构（MLI）。 MLI包括多个保险丝连接和接合连接功能。钝化层形成在MLI上方并被图案化以形成开口，其中每个开口与保险丝连接或接合连接特征中的一个对准。在钝化层和开口中形成导电层。将导电层图案化以形成结合特征和熔丝结构。每个接合特征与接合连接特征之一接触，并且每个熔断器结构与两个熔断器连接特征接触。在熔丝结构之上形成盖电介质层，并将其图案化以暴露粘合特征中的至少一个，同时保留熔丝结构。

73. 发明申请

US20100078728A1 RAISE S/D FOR GATE-LAST ILD0 GAP FILLING 审中-公开
标题翻译： GIS-LAST ILD0 GAP填充的RAISE S / D
公开(公告)号：US20100078728A1
公开(公告)日：2010-04-01
申请号：US12546475
申请日：2009-08-24
申请人： Hou-Ju Li , Chung Long Cheng , Kong-Beng Thei , Harry Chuang
发明人： Hou-Ju Li , Chung Long Cheng , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823814 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66628 , H01L29/7848
摘要： The present disclosure provides an integrated circuit having metal gate stacks. The integrated circuit includes a semiconductor substrate; a gate stack disposed on the semiconductor substrate, wherein the gate stack includes a high k dielectric layer and a first metal layer disposed on the high k dielectric layer; and a raised source/drain region configured on a side of the gate stack and formed by an epitaxy process, wherein the semiconductor substrate includes a silicon germanium (SiGe) feature underlying the raised source/drain region.
摘要翻译：本公开提供了具有金属栅极堆叠的集成电路。集成电路包括半导体衬底; 设置在所述半导体衬底上的栅极堆叠，其中所述栅极堆叠包括高k电介质层和设置在所述高k电介质层上的第一金属层; 以及构造在所述栅极堆叠侧并通过外延工艺形成的凸起的源极/漏极区域，其中所述半导体衬底包括位于所述升高的源极/漏极区域下方的硅锗（SiGe）特征。

74. 发明授权

US07364957B2 Method and apparatus for semiconductor device with improved source/drain junctions 有权
公开(公告)号：US07364957B2
公开(公告)日：2008-04-29
申请号：US11490012
申请日：2006-07-20
申请人： Kong-Beng Thei , Chung Long Cheng , Harry Chuang
发明人： Kong-Beng Thei , Chung Long Cheng , Harry Chuang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/331
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L29/105 , H01L29/1083 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

75. 发明申请

US20120196434A1 E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit 有权
标题翻译：嵌入式存储器电路的电可编程冗余中的电熔丝结构设计
公开(公告)号：US20120196434A1
公开(公告)日：2012-08-02
申请号：US13443550
申请日：2012-04-10
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L21/02
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

76. 发明授权

US07868386B2 Method and apparatus for semiconductor device with improved source/drain junctions 有权
标题翻译：具有改善的源极/漏极结的半导体器件的方法和装置
公开(公告)号：US07868386B2
公开(公告)日：2011-01-11
申请号：US12058997
申请日：2008-03-31
申请人： Kong-Beng Thei , Chung Long Cheng , Harry Chuang
发明人： Kong-Beng Thei , Chung Long Cheng , Harry Chuang
IPC分类号： H01L23/58 , H01L29/76 , H01L29/94
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L29/105 , H01L29/1083 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.
摘要翻译：公开了一种具有改善的源极/漏极结的半导体器件和用于制造该器件的方法。优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度与45度之间。另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

77. 发明申请

US20100052070A1 NOVEL DEVICE SCHEME OF HKMG GATE-LAST PROCESS 有权
标题翻译： HKMG GATE-LAST过程的新设备方案
公开(公告)号：US20100052070A1
公开(公告)日：2010-03-04
申请号：US12536878
申请日：2009-08-06
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/66545
摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.
摘要翻译：本公开提供了制造半导体器件的金属栅叠层的方法。该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

78. 发明授权

US08058119B2 Device scheme of HKMG gate-last process 有权
标题翻译： HKMG最终进程的设备方案
公开(公告)号：US08058119B2
公开(公告)日：2011-11-15
申请号：US12536878
申请日：2009-08-06
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/66545
摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.
摘要翻译：本公开提供了制造半导体器件的金属栅叠层的方法。该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

79. 发明授权

US08008145B2 High-K metal gate structure fabrication method including hard mask 有权
标题翻译：高K金属栅极结构制造方法包括硬掩模
公开(公告)号：US08008145B2
公开(公告)日：2011-08-30
申请号：US12270466
申请日：2008-11-13
申请人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.
摘要翻译：提供一种制造包括高k金属栅极结构的半导体器件的方法。提供了包括伪栅极结构（例如，牺牲多晶硅栅极），覆盖在虚拟栅极结构上的第一和第二硬掩模层的衬底。在一个实施例中，在基底上形成应变区域。形成应变区后，可以除去第二硬掩模层。可以形成源极/漏极区域。然后在衬底上形成ILD层。 CMP工艺可以使用第一硬掩模层作为停止层来平坦化ILD层。 CMP工艺可以继续去除第一硬掩模层。然后去除虚拟栅极结构并提供金属栅极。

80. 发明授权

US07927943B2 Method for tuning a work function of high-k metal gate devices 有权
标题翻译：用于调谐高k金属栅极器件功能的方法
公开(公告)号：US07927943B2
公开(公告)日：2011-04-19
申请号：US12488960
申请日：2009-06-22
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成第一和第二晶体管，第一晶体管具有包括第一虚拟栅极的第一栅极结构，第二晶体管具有第二栅极结构包括第二伪栅极，去除第一和第二伪栅极，从而分别形成第一沟槽和第二沟槽，形成第一金属层以部分地填充在第一和第二沟槽中，去除第一沟槽内的第一金属层形成第二金属层以部分地填充在第一和第二沟槽中，形成第三金属层以部分地填充在第一和第二沟槽中，回流第二金属层和第三金属层，以及形成第四金属层以填充在第一和第二个沟槽的剩余部分。

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