专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20080116578A1 Initiation layer for reducing stress transition due to curing 审中-公开
标题翻译：起始层，用于减少由于固化而引起的应力转变
公开(公告)号：US20080116578A1
公开(公告)日：2008-05-22
申请号：US11602857
申请日：2006-11-21
申请人： Kuan-Chen Wang , Zhen-Cheng Wu , Fang Wen Tsai , Yih-Hsing Lo , I-I Chen , Tien-I Bao , Shwang-Ming Jeng
发明人： Kuan-Chen Wang , Zhen-Cheng Wu , Fang Wen Tsai , Yih-Hsing Lo , I-I Chen , Tien-I Bao , Shwang-Ming Jeng
IPC分类号： H01L23/50 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76825 , H01L21/76832 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an etch stop layer over a substrate; a UV blocker layer on the etch stop layer, wherein the UV blocker layer has a high extinction coefficient; and a low-k dielectric layer on the UV blocker layer.
摘要翻译：集成电路包括在衬底上的蚀刻停止层; 在所述蚀刻停止层上的UV阻挡层，其中所述UV阻挡层具有高消光系数; 和UV阻挡层上的低k电介质层。

72. 发明授权

US07365026B2 CxHy sacrificial layer for cu/low-k interconnects 有权
标题翻译： CxHy用于cu / low-k互连的牺牲层
公开(公告)号：US07365026B2
公开(公告)日：2008-04-29
申请号：US11048215
申请日：2005-02-01
申请人： Shwang-Ming Jeng , Ming Ling Yeh , Tien-I Bao , Keng-Chu Lin
发明人： Shwang-Ming Jeng , Ming Ling Yeh , Tien-I Bao , Keng-Chu Lin
IPC分类号： H01L21/469 , H01L23/58
CPC分类号： H01L21/02274 , H01L21/02118 , H01L21/0212 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02134 , H01L21/02137 , H01L21/02203 , H01L21/312 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76831
摘要： A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3, using a PECVD process. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing low-k dielectric damage caused by plasma processing or etching. Other embodiments comprise a semiconductor device having a low-k dielectric, wherein the low-k dielectric has carbon-adjusted dielectric region adjacent a trench sidewall and a bulk dielectric region. In preferred embodiments, the carbon-adjusted dielectric region has a carbon concentration not more than about 5% less than in the bulk dielectric region.
摘要翻译：提供涉及低k电介质的半导体制造方法。该方法包括在低k电介质的表面上沉积一般组合物C x H y Y y的烃。烃层通过使前体材料，优选C 2 H 4 H 3或（CH 3）3 H 2， CHC 6 6 H 3 CH 3，使用PECVD法。根据本发明的实施例，碳扩散到低k电介质中，由此降低由等离子体处理或蚀刻引起的低k电介质损伤。其他实施例包括具有低k电介质的半导体器件，其中低k电介质具有邻近沟槽侧壁和大块电介质区域的碳调节介电区域。在优选的实施方案中，碳调节的电介质区域的碳浓度比体电介质区域的碳浓度小约不超过约5％。

73. 发明申请

US20050242430A1 Multi-level semiconductor device with capping layer with improved adhesion 有权
标题翻译：具有覆盖层的多层半导体器件具有改善的附着力
公开(公告)号：US20050242430A1
公开(公告)日：2005-11-03
申请号：US10836297
申请日：2004-04-30
申请人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
发明人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76826 , H01L21/76825 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multi-layer semiconductor device including copper interconnects with improved interlayer adhesion and a method for forming the same, the method including providing a semiconductor substrate comprising a dielectric insulating layer comprising copper containing interconnects the dielectric insulating layer and copper containing interconnects comprising an exposed surface; forming a first capping layer on the exposed surface; providing a treatment on the first capping layer to increase interface adhesion between the capping layer and the dielectric insulating layer; and, forming a second capping layer on the first capping layer.
摘要翻译：一种包括具有改进的层间粘合性的铜互连的多层半导体器件及其形成方法，所述方法包括提供半导体衬底，所述半导体衬底包括包含铜的介电绝缘层，所述电介质绝缘层将所述介电绝缘层和包含暴露表面的含铜互连互连; 在所述暴露表面上形成第一覆盖层; 在所述第一盖层上提供处理以增加所述封盖层和所述介电绝缘层之间的界面粘附; 并且在所述第一覆盖层上形成第二覆盖层。

74. 发明授权

US06887790B1 Method of forming dummy copper plug to improve low k structure mechanical strength and plug fill uniformity 有权
标题翻译：形成假铜塞以改善低k结构机械强度和塞填充均匀性的方法
公开(公告)号：US06887790B1
公开(公告)日：2005-05-03
申请号：US10199856
申请日：2002-07-19
申请人： Tien-I Bao , Bi-Trong Chen , Ying-Ho Chen
发明人： Tien-I Bao , Bi-Trong Chen , Ying-Ho Chen
IPC分类号： H01L21/44 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76838 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided for the creation of dummy plugs in support of creating a robust structure of overlying interconnect traces. A pattern of holes for dummy plugs is etched stopping at an etch stop layer, the etch stop layer is then removed from the bottom of the holes that have been created whereby this removal is extended into an underlying layer of insulating material. The pattern of holes is filled with a metal, preferably copper, excess metal is removed by methods of Chemical Mechanical Polishing, leaving in place a pattern of metal plugs that penetrate through layers of insulation material and through layers of etch stop material and into an underlying layer of semiconductor material.
摘要翻译：提供了一种新的方法来创建虚拟插头，以支持创建上层互连线路的稳健结构。在蚀刻停止层处蚀刻停止用于虚拟插头的孔的图案，然后从已经形成的孔的底部去除蚀刻停止层，由此将该去除延伸到下面的绝缘材料层中。孔的图案填充有金属，优选铜，通过化学机械抛光的方法除去多余的金属，留下穿过绝缘材料层并通过蚀刻停止材料层的金属塞的图案，并进入下面的半导体材料层。

75. 发明申请

US20050090122A1 SIOC PROPERTIES AND ITS UNIFORMITY IN BULK FOR DAMASCENE APPLICATIONS 有权
标题翻译： SIOC属性及其在大容量应用中的均匀性
公开(公告)号：US20050090122A1
公开(公告)日：2005-04-28
申请号：US10692030
申请日：2003-10-23
申请人： Syun-Ming Jang , Chung-Chi Ko , Tien-I Bao , Lih-Ping Li , Ai-Sen Liu
发明人： Syun-Ming Jang , Chung-Chi Ko , Tien-I Bao , Lih-Ping Li , Ai-Sen Liu
IPC分类号： H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/76835 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/0234 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76829
摘要： A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.
摘要翻译：一种形成低k电介质材料层的方法，包括以下步骤。第一介电材料子层形成在衬底上。第一介电材料子层用能量处理处理，以在第一介电材料子层的上表面上形成硬化层。第二电介质子层形成在硬化层上，其中第一介电子层，硬化层和第二电介质子层包括低k电介质材料层。以及由此形成的双镶嵌结构和介电材料结构。

76. 发明申请

US20050062164A1 Method for improving time dependent dielectric breakdown lifetimes 审中-公开
标题翻译：改善时间依赖介电击穿寿命的方法
公开(公告)号：US20050062164A1
公开(公告)日：2005-03-24
申请号：US10668702
申请日：2003-09-23
申请人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
发明人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L29/06 , H01L29/40 , H01L29/00
CPC分类号： H01L21/76825 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/022 , H01L21/02304 , H01L21/02315 , H01L21/02351 , H01L21/3121 , H01L21/31633 , H01L21/3185 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L29/405
摘要： The present disclosure provides a method for increasing a time dependent dielectric breakdown lifetime of a semiconductor device and a structure fabricated using this method. The method includes depositing a first layer and then forming a glue layer on the first layer. A treatment process, which may use a plasma or an electron beam, is performed on the glue layer. The treatment process improves an interface between the glue layer and the first layer. The treatment process may also affect electrical properties of the glue layer. A second layer may then be deposited onto the treated glue layer.
摘要翻译：本公开提供了一种用于增加半导体器件的时间依赖介电击穿寿命和使用该方法制造的结构的方法。该方法包括沉积第一层然后在第一层上形成胶层。在胶层上进行可以使用等离子体或电子束的处理工艺。处理过程改善了胶层和第一层之间的界面。处理过程也可能影响胶层的电性能。然后可以将第二层沉积在经处理的胶层上。

77. 发明申请

US20050048795A1 Method for ultra low-K dielectric deposition 审中-公开
标题翻译：超低K电介质沉积方法
公开(公告)号：US20050048795A1
公开(公告)日：2005-03-03
申请号：US10649566
申请日：2003-08-27
申请人： Chung-Chi Ko , Yung-Cheng Lu , Tien-I Bao , Hui-Lin Chang , Syun-Ming Jang
发明人： Chung-Chi Ko , Yung-Cheng Lu , Tien-I Bao , Hui-Lin Chang , Syun-Ming Jang
IPC分类号： H01L21/312 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02271 , H01L21/02126 , H01L21/02282 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/312 , H01L21/3121 , H01L21/7682
摘要： The present invention provides a method of forming a semiconductor structure having an ultra low-K dielectric material that adheres well to the substrate. The method includes depositing a low-K material on the top surface of a substrate at a low temperature of no more than 250° by a CVD or spin-on process. The dielectric material is then cured by placing the substrate with the dielectric film in an environment where the temperature is regulated at about 400° or less as the dielectric film is being subjected to a plasma treatment or an E-beam treatment or UV treatment. The environment may further include one or more gases or a mixture of gases selected from the group consisting of H2, N2, NH3, CO2, all hydride gases and a mixture of these gases.
摘要翻译：本发明提供一种形成半导体结构的方法，所述半导体结构具有与基底良好粘合的超低K电介质材料。该方法包括通过CVD或旋涂工艺在低于250°的低温下在衬底的顶表面上沉积低K材料。然后通过将介质膜放置在介质膜经受等离子体处理或电子束处理或UV处理的温度调节在约400°或更小的环境中来固化电介质材料。环境可以进一步包括选自H 2，N 2，NH 3，CO 2，所有氢化物气体和这些气体的混合物的一种或多种气体或气体混合物。

78. 发明授权

US06667249B1 Minimizing coating defects in low dielectric constant films 有权
标题翻译：最小化低介电常数膜中的涂层缺陷
公开(公告)号：US06667249B1
公开(公告)日：2003-12-23
申请号：US10101655
申请日：2002-03-20
申请人： Yu-Hui Chen , Tien-I Bao , Yao-Yi Cheng
发明人： Yu-Hui Chen , Tien-I Bao , Yao-Yi Cheng
IPC分类号： H01L2131
CPC分类号： H01L21/02118 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02307 , H01L21/312 , H01L21/3122 , H01L21/31695 , H01L21/76801 , H01L21/76829
摘要： A method of coating a low dielectric constant material layer wherein the wafer surface is pre-wetted using a solvent to prevent or reduce coating defects is described. A semiconductor substrate is provided wherein a top surface of the semiconductor substrate may have surface defects. A solvent is coated overlying the top surface of the semiconductor substrate. A low dielectric constant material layer is coated overlying the solvent wherein the solvent covers the surface defects thereby preventing defects in the low dielectric constant material layer.
摘要翻译：描述了一种涂覆低介电常数材料层的方法，其中晶片表面使用溶剂预先润湿以防止或减少涂层缺陷。提供半导体衬底，其中半导体衬底的顶表面可能具有表面缺陷。将溶剂涂覆在半导体衬底的顶表面上。将低介电常数材料层涂覆在溶剂上，其中溶剂覆盖表面缺陷从而防止低介电常数材料层中的缺陷。

79. 发明授权

US06620745B2 Method for forming a blocking layer 有权
标题翻译：形成阻挡层的方法
公开(公告)号：US06620745B2
公开(公告)日：2003-09-16
申请号：US10051589
申请日：2001-10-19
申请人： Syan-Mang Jang , Tien-I Bao , Lain-Jong Li , Shwang-Ming Jeng
发明人： Syan-Mang Jang , Tien-I Bao , Lain-Jong Li , Shwang-Ming Jeng
IPC分类号： H01L2131
CPC分类号： H01L21/76829 , H01L21/3105 , H01L21/31144 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76832
摘要： A method is provided for forming a blocking layer in a multilayer semiconductor device for blocking diffusion of a chemical species including the steps of providing an insulating layer including a target surface for forming a metal nitride layer thereon said insulating layer forming a portion of a multilayer semiconductor device; treating the target surface with an RF generated plasma to cause a density increase over a thickness adjacent to and including a target surface sufficient to reduce a diffusion rate of chemical species therethrough; forming at least one metal nitride layer over the target surface; and, carrying out a photolithographic process wherein the surface of the at least one metal nitride layer is patterned for etching.
摘要翻译：提供一种用于在用于阻挡化学物质扩散的多层半导体器件中形成阻挡层的方法，包括以下步骤：提供包括用于在其上形成金属氮化物层的靶表面的绝缘层，所述绝缘层形成多层半导体的一部分设备; 用RF产生的等离子体处理目标表面以使得在邻近并包括目标表面的厚度上产生足够的浓度以减少化学物质通过其的扩散速率的密度增加; 在目标表面上形成至少一个金属氮化物层; 以及执行光刻工艺，其中至少一个金属氮化物层的表面被图案化以进行蚀刻。

80. 发明授权

US06518183B1 Hillock inhibiting method for forming a passivated copper containing conductor layer 有权
标题翻译：用于形成钝化含铜导体层的起丘抑制方法
公开(公告)号：US06518183B1
公开(公告)日：2003-02-11
申请号：US09947782
申请日：2001-09-06
申请人： Weng Chang , Tien-I Bao , Ying-Ho Chen , Syun-Ming Jang
发明人： Weng Chang , Tien-I Bao , Ying-Ho Chen , Syun-Ming Jang
IPC分类号： H01L2144
CPC分类号： H01L21/76883 , H01L21/76834
摘要： Within a method for fabricating a microelectronic fabrication having formed therein a copper containing conductor layer passivated with a passivation layer, there is first: (1) pre-heated the copper containing conductor layer to a temperature of from about 300 to about 450 degrees centigrade for a time period of from about 30 to about 120 seconds to form a pre-heated copper containing conductor layer; and then (2) plasma treated the pre-heated copper containing conductor layer within a reducing plasma to form a plasma treated pre-heated copper containing conductor layer; prior to (3)forming upon the plasma treated pre-heated copper containing conductor layer the passivation layer. The foregoing process sequence provides for attenuated hillock defects within the plasma treated pre-heated copper containing conductor layer when forming the passivation layer thereupon.
摘要翻译：在其中形成有钝化层钝化的含铜导体层的微电子制造方法中，首先：（1）将含铜导体层预热至约300至约450摄氏度的温度，用于约30至约120秒的时间段以形成预热的含铜导体层; 然后（2）在还原等离子体中等离子体处理预热的含铜导体层，以形成等离子体处理的预热含铜导体层; 在（3）在等离子体处理的预热含铜导体层上形成钝化层之前。当在其上形成钝化层时，上述工艺顺序提供等离子体处理的预热含铜导体层内的衰减的小丘缺陷。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式