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71. 发明专利

JPH06244354A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06244354A
公开(公告)日：1994-09-02
申请号：JP3172593
申请日：1993-02-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OTSUKA KANJI , MIZUKAMI MASAO , SHIRAI MASAYUKI , MIWA TAKASHI , OKINAGA TAKAYUKI , SUZUKI HIROMICHI , MATSUNAGA TOSHIHIRO
IPC分类号： H01L23/50
摘要： PURPOSE:To provide a differential-interface LSI capable of processing signals with high clock frequency between LSI's and making a package smaller. CONSTITUTION:A semiconductor integrated circuit device includes a differential- interface LSI for transmitting a pulse signal between LSI's, and a lead 5 is made up of an upper-layer lead 5a and a lower-layer lead 5b, which are electrically insulated from each other through a polyimide foil (insulating film) 6.

72. 发明专利

JPH05136307A LEAD FRAME FORMATION AND SEMICONDUCTOR DEVICE FORMED BY IT 失效
公开(公告)号：JPH05136307A
公开(公告)日：1993-06-01
申请号：JP29732091
申请日：1991-11-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , SHIRAI MASAYUKI , EMATA KOJI , HORIUCHI HITOSHI , SUZUKI HIROMICHI
IPC分类号： H01L23/50
摘要： PURPOSE:To provide lead frame formation which improves the processing accuracy and the reliability of a semiconductor device formed by the lead frame formation. CONSTITUTION:A lead frame plate material is prepared, the part of the plate thickness is etched on an inner lead 3, between inner leads 3 and between outer leads 4 and the rest of the plate thickness between the inner leads 3 and between the outer leads 4 are punched out. Therefore, since the plate thickness of the inner lead 3 becomes thin, the process accuracy of the inner lead 3 is improved. Since the plate between the inner leads 3 and between the outer leads 4 are etched to the uniform plate thickness, the process accuracy for punching out is improved. The plate thickness of the outer lead 4 is allowed to be thick independently from the plate thickness of the inner lead 3 and the mechanical strength of the outer lead 4 is ensured.

73. 发明专利

JPH04260343A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04260343A
公开(公告)日：1992-09-16
申请号：JP2130591
申请日：1991-02-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , UCHIUMI YASUYUKI , OTSUKA KANJI , EMATA KOJI , SUZUKI HIROMICHI , KUWATA MAKOTO
IPC分类号： H01L21/60
摘要： PURPOSE:To improve reflow crack resistance of a tape carrier package. CONSTITUTION:Leads 2 formed on one surface of an insulating film 1 is connected with a semiconductor chip 4 by a TAB method. In a tape carrier package wherein a semiconductor chip 4 is sealed with a package main body 6 of synthetic resin which has an external size smaller than the insulating film 1, a notch 7 is formed in the insulating film 1 inside the package main body 6.

74. 发明专利

JPH04260342A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04260342A
公开(公告)日：1992-09-16
申请号：JP2130491
申请日：1991-02-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , UCHIUMI YASUYUKI , OTSUKA KANJI , HORIUCHI HITOSHI , SUZUKI HIROMICHI
IPC分类号： H01L21/60
摘要： PURPOSE:To improve the reliability and the manufacturing yield of an area TAB, by preventing the generation of voids in the gap between a semiconductor chip and an insulative film. CONSTITUTION:In the title semiconductor integrated circuit device of an area TAB system, a through hole 6 is formed in a part of an insulating film 1 in the region facing a semiconductor chip 3.

75. 发明专利

JPH04181761A LEAD FRAME, AND MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING IT 失效
公开(公告)号：JPH04181761A
公开(公告)日：1992-06-29
申请号：JP31058590
申请日：1990-11-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , HONDA ATSUSHI , HORIUCHI HITOSHI , SUZUKI HIROMICHI , OTSUKA KANJI
IPC分类号： H01L23/50
摘要： PURPOSE:To prevent a defect such as the bend of a lead or the like caused when a tie bar is cut and to make a lead pitch fine by a method wherein the tie bar which connects leads is abolished. CONSTITUTION:A die pad 2 on which a semiconductor chip is loaded is arranged in the central part of a lead frame 1. A plurality of leads 3 are arranged at the outside of the die pad 2 so as to surround the die pad 2. Suspension leads 4 which support the die pad 2 are installed at four corners of the die pad 2. A tie bar which supports the leads 3 is not installed at the halfway part of the leads 3. The outermost circumferential part is composed of an outer frame 5 and an inner frame 6; guide holes 7 used to position the lead frame in a prescribed position at a molding metal mold are formed in the outer frame 5. Since the tie bar is abolished in this manner, a tie-bar cutting process is not required after a package main body has been molded. Thereby, it is possible to prevent a defect such as the bend of a lead or the like caused when the tie bar is cut and to make a lead pitch fine.

76. 发明专利

JPH04155853A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04155853A
公开(公告)日：1992-05-28
申请号：JP28092690
申请日：1990-10-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NAKAMURA KOJI , HONDA ATSUSHI , OKINAGA TAKAYUKI , MATSUGAMI SHOJI
IPC分类号： H01L23/36
摘要： PURPOSE:To enable a semiconductor integrated circuit device to be improved in heat dissipating effect by a method wherein a semiconductor chip bonded to a package substrate is sealed up with a cap, and a heat dissipating protrusion is provided to the inner wall of tire cap which approximates to or comes into contact with the primary face of a semiconductor chip. CONSTITUTION:A semiconductor circuit formed in a semiconductor chip 4 is electrically connected to one end of a wiring pattern 6a formed on a package board 2 through the intermediary of a bonding wire 5. A cap 11a is bonded to the upside of the package board 2 with adhesive agent or the like to seal up the semiconductor chip 4. A heat dissipating protrusion 12a is provided to the center of the inner wall of the cap 11a. The heat dissipating protrusion 12a is formed in one piece with the cap 11a and arranged so as to enable its top face to be located adjacent to the primary face of the semiconductor chip 4. Heat released from the semiconductor chip 4 in operation is diffused into a silicone get and transmitted to the heat dissipating protrusion 12a, and dissipated outside as transmitted to a heat sink 13 via the cap 11a from the protrusion 12a.

77. 发明专利

JPH0496257A PIN GRID ARRAY TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0496257A
公开(公告)日：1992-03-27
申请号：JP20598990
申请日：1990-08-03
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , OTSUKA KANJI , SHIRAI MASAYUKI , MATSUGAMI SHOJI , OGUMA HIROSHI
IPC分类号： H01L23/12 , H01L21/60
摘要： PURPOSE:To speed up the operation of a title device and promote multiple pin construction by extending onto a chip one end of a wiring formed on an insulating substrate, and electrically connecting an electrode pad provided at the center on a chip integrated circuit formation surface. CONSTITUTION:An insulating film 9 on which a wiring 3 is formed is bonded to an insulating substrate 2 and to a chip 7. There is previously provided an opening 10 at a portion corresponding to an electrode pad of the chip 7 through the insulating film 9, and the electrode pad exposed to the bottom of the insulating film 9 and the wiring 3 are connected with each other through a wire 8 such as Au. The chip 7 located in a cavity 6 are sealed with caps 11a, 11b. The caps 11a, 11b comprise synthetic resin and are joined with the insulating substrate 2 via a bonding agent 12 such as silicone rubber. A pin grid array 1 constructed as above mounts thereon the multiple pin chip 7 including electrode pads thereon along the peripheral edge and at the central portion, and hence construction of the pin grid array 1 with multiple pins is promoted.

78. 发明专利

JPH03116768A LEAD FRAME AND ITS MANUFACTURE 失效
公开(公告)号：JPH03116768A
公开(公告)日：1991-05-17
申请号：JP25324489
申请日：1989-09-28
申请人： DAINIPPON PRINTING CO LTD , HITACHI LTD , HITACHI VLSI ENG
发明人： KATO TSUNENORI , MURAKAMI HAJIME , SUZUKI HIROMICHI , OKINAGA TAKAYUKI , EMATA KOJI , HORIUCHI HITOSHI
IPC分类号： H01L23/50 , H01L23/495
摘要： PURPOSE:To relax the stress arising during each heat treatment of a lead frame so as to reduce the warp of the lead frame by putting an adhesive film or a resin film partially in sections between a lead frame unit and a board. CONSTITUTION:A lead frame 1 is constituted in three-layer structure out of a lead frame unit 2, an adhesive film or a resin film 3, which has adhesives on both sides, and a board 4 consisting of metal or resin, which is joined to the lead frame unit through said film. The resin film 3 is interposed at minimum neccessary plural specified places a, a,... on the lead frame unit 2. For the adhesive film, for example, thermosetting resin is formed into film shape, and for the resin film, for example, based on a polyimide film, thermosetting resin is bonded to both sides of it, thus these are formed into the shape of a both- sided tape. For the making of the lead frame 1, plural pieces of adhesive films or resin films 3 are stuck to the lead frame unit 2 by a taping machine, or the like to begin with, and the board 4 is arranged on the bottom of the resin film 3 while performing the positioning of the unit 2 highly accurately, and then this board is pressure adhered.

79. 发明专利

JPH0382147A SEMICONDUCTOR DEVICE AND FORMATION OF LEAD FRAME THEREOF 失效
公开(公告)号：JPH0382147A
公开(公告)日：1991-04-08
申请号：JP21738989
申请日：1989-08-25
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HOKKAI SEMICONDUCTOR
发明人： TATE HIROSHI , OTSUKA KANJI , HORIUCHI HITOSHI , OKINAGA TAKAYUKI , HASEBE HAJIME
IPC分类号： H01L21/60 , H01L23/50
摘要： PURPOSE:To form widened parts wider than a lead width, to use these parts as bonding parts and to make possible an increase in the integration of a semiconductor device and a reduction in the size of the device by a method wherein the point parts of leads provided at a targeted lead pitch are widened while a prescribed space between leads is secured. CONSTITUTION:A lead frame 1 is first processed at a targeted lead pitch. The processing of this lead frame 1 may be performed by any system of a punching system and an etching system. Tabs 6 are provided on the inner side of the frame 1. Moreover, in order to prevent the positional deviation between leads and the tortion and deformation of the leads, the spaces between the leads are supported by a film 5, such as of epoxy resin, polyimide or the like. Then, the leads in the vicinities of the tabs 6, that is, bonding parts are pressed by a press or the like and widened parts 4 are formed. Moreover, the parts 4 are cut from the tabs 6 and bonding surfaces are polished according to the need or a bonding metal (Al and Ag) film is formed.

80. 发明专利

JPH02285646A RESIN SEALED SEMICONDUCTOR DEVICE AND FORMATION THEREOF 失效
公开(公告)号：JPH02285646A
公开(公告)日：1990-11-22
申请号：JP10586389
申请日：1989-04-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HORIUCHI HITOSHI , MURAKAMI HAJIME , SUZUKI HIROMICHI , HASEBE HAJIME , OTSUKA KANJI , SHIRAI MASAYUKI , OKINAGA TAKAYUKI , EMATA KOJI
IPC分类号： H01L21/60 , H01L23/495 , H01L23/498
摘要： PURPOSE:To acquire such merits as simplification of structure, reduction of manufacturing processes, enhancement of humidity resistance and electrical reliability, etc., by a method wherein a semiconductor pellet is arranged in the central part on a film substrate comprising insulating materials laminated on a metallic sheet while inner leads as they remain electrically isolated from the metallic sheet are arranged around the film substrate. CONSTITUTION:Within a semiconductor device 1 wherein a semiconductor pellet 1 is arranged in the region encircled by the ends of inner leads 3A radially arranged while the outer terminals of the pellet 2 are connected to inner leads 3A to be sealed up with resin 5, the semiconductor pellet 2 is arranged almost in the central part of a film substrate 4; simultaneously, the inner leads 3A are arranged as they remain electrically isolated from the metallic sheets 4B of the substrate 4 on the encircling film substrate 4; and finally the outer terminals of the semiconductor pellet 2 between the outer terminal for power supply and the central part of the metallic sheet 4B of the film substrate 4 as well as the inner leads 3A between the inner lead for power supply and the peripheral part of the metallic sheet 4B are respectively connected by bonding wires 6.

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