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71. 发明专利

JPH08305563A DATA PROCESSING UNIT 失效
公开(公告)号：JPH08305563A
公开(公告)日：1996-11-22
申请号：JP11276795
申请日：1995-05-11
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , HATANO YUJI
IPC分类号： G06F9/32 , G06F9/30
摘要： PURPOSE: To provide the data processing unit to support a conditional arithmetic instruction in which the processing efficiency is improved without causing problems such as performance deterioration due to a limit of a degree of freedom of operands or kinds of instructions and increase in program memory capacity due to increase in an instruction code length. CONSTITUTION: The processing unit is provided with a condition selection means selecting at least one condition among plural conditions to be used for a conditional arithmetic instruction, a conditional information storage means 103 (CSR) storing condition information selected by the condition selection means, and a means 104 (CCR) storing information denoting property of the result of arithmetic operation based on at least the selected condition and the conditional arithmetic instruction has a function to execute required arithmetic processing one of selected conditions is designated and the condition is established.

72. 发明专利

JPH07282237A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH07282237A
公开(公告)日：1995-10-27
申请号：JP7182194
申请日：1994-04-11
申请人： HITACHI LTD
发明人： WATABE TAKAO , NAKAGOME YOSHINOBU , ISHIKURA KAZUO , NAKAGAWA TETSUYA , KIUCHI ATSUSHI
IPC分类号： G06T1/20 , G06F13/00 , G06F15/167 , G06F15/80 , G06F17/10 , G06F17/15 , G06T5/20 , G11C7/10
摘要： PURPOSE:To obtain the semiconductor integrated circuit which performs arithmetic processing using two-dimensional data at a high speed with high parallelism. CONSTITUTION:This semiconductor integrated circuit is equipped with a two-dimensional memory array MAR, a parallel data transfer circuit TRC which transfers data read out in parallel through data lines by selecting word lines of the two-dimensional memory array MAR to an arithmetic circuit group PE in parallel, and the arithmetic circuit group PE which performs arithmetic processing in parallel by using the data transferred from the parallel data transfer circuit TRC; and the individual arithmetic circuits PE can access plural successive word lines and data lines of the two-dimensional memory array MAR through the parallel data transfer circuit TRC, and the ranges of data lines of the two-dimensional memory array MAR that plural adjacent arithmetic circuits PE can access overlap with each other. Thus, the ranges of the data lines that the adjacent arithmetic circuits PE can access overlap with each other, so convolution arithmetic, etc., can be performed in parallel for two-dimensional data stored in the two-dimensional memory array MAR.

73. 发明专利

JPH07175666A DATA PROCESSOR AND INTERRUPTION REQUEST PROCESSING METHOD FOR THE SAME 失效
公开(公告)号：JPH07175666A
公开(公告)日：1995-07-14
申请号：JP22695994
申请日：1994-09-21
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI
IPC分类号： G06F11/22 , G06F1/32 , G06F9/46 , G06F9/48 , G06F13/24 , G06F15/78
摘要： PURPOSE:To keep the operating mode of an arbitrary data processor before and after any arbitrary interruption request. CONSTITUTION:The data processor is provided with an interruption controller 2600, data memory 1900 equipped with a condition code register, condition code register controller, condition code stack register and stack area, data processing unit and interruption request decoder, the interruption controller 2600 receives one interruption request signal and an interruption request signal containing plural standard interruption request signal, the condition code register stores a condition code value containing a data processor mode control value and the data processing unit performs a data processing operation. When the data processor mode control value is set at a fixed sleep mode value or a software waiting mode value, this data processing operation is stopped but when the data processor mode control value is set in a fixed execution mode, the operation is started again.

74. 发明专利

JPH07168714A DIGITAL SIGNAL PROCESSOR AND METHOD FOR EXECUTING INSTRUCTION USING THE SAME 失效
公开(公告)号：JPH07168714A
公开(公告)日：1995-07-04
申请号：JP22856194
申请日：1994-09-26
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , UMAJI TORU , NAKAGAWA TETSUYA , KANEKO KENJI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
摘要： PURPOSE:To provide a digital signal processor(DSP) for defining the same data processing or data transfer operation and the DSP for executing a RISC class instruction. CONSTITUTION:A DSP 1100 is composed of an instruction memory 1400 and an instruction decoder 1600. The instruction memory 1400 stores the sequence of instruction words including a DSP instruction word and a RISC instruction word. Each instruction word is provided with a type code field TY for designating whether the instruction is a RISC instruction or a DSP instruction. The prescribed RISC instruction word is provided with a different source and a destination field for designating register positions for a data source and a data destination. One of the source and the destination field in the prescribed RISC instruction word is provided with bits more than those of a correspondent field in the prescribed DSP instruction word at least.

75. 发明专利

JPH03223978A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPH03223978A
公开(公告)日：1991-10-02
申请号：JP29969390
申请日：1990-11-07
申请人： HITACHI LTD
发明人： UBUSAWA MITSURU , KIUCHI ATSUSHI , NAKAGAWA TETSUYA
IPC分类号： G09G5/02 , G06T15/40 , G09G5/36 , G11C11/401
摘要： PURPOSE:To omit the need to perform the replacement of data on the drawing arithmetic result based on the data value deciding result within a drawing arithmetic unit by outputting the data on the value deciding result of the depth data to the outside of the drawing arithmetic unit. CONSTITUTION:The processor is provided with a polygon data memory 101 to store the picture element data, a Z-axis data memory 102 which stores the depth data, a data supply means 103 which supplies the 3-dimensional data showing a position, the arithmetic means 104 and 107, and a control means 123. Then the depth data, the R data, the G data, and the B data are generated with interpolation and in parallel with each other. The value deciding processing is carried out via a pipeline operation for the new depth data, i.e., the result of generation of those data. Thus it is possible to add the picture element data to four types of data consisting of the values of Z coordinate and to perform the comparison at a high speed among these Z coordinate values.

76. 发明专利

JPH03150646A ADDRESS CONTROLLER 失效
公开(公告)号：JPH03150646A
公开(公告)日：1991-06-27
申请号：JP28887589
申请日：1989-11-08
申请人： HITACHI LTD
发明人： NAKAGAWA TETSUYA , KIUCHI ATSUSHI , UMAJI TORU
IPC分类号： G06F12/02
摘要： PURPOSE:To efficiently support a high level language by giving an address register enough bit length to access all storage areas of plural memory banks. CONSTITUTION:The bit length of an address register 3 in each of address units 11a and 11b is extended by one bit so that all of the data memory spaces consisting of two pages can be linearly indicated. An address bus route switching circuit 6 is provided between two address units 11a and 11b and data memories 8a, and 8b of two pages to prevent specific address units 11a and 11b from being attached to a specific data page. Consequently, arbitrary address registers 3 and data memories 8a and 8b of arbitrary pages can be connected, and each address register 3 has enough length to linearly indicate all of the data memory space. As the result, all of the data memory space is directly accessed with one address register 3. Thus, the high level language is efficiently supported.

77. 发明专利

JPH01166221A INFORMATION PROCESSOR 失效
公开(公告)号：JPH01166221A
公开(公告)日：1989-06-30
申请号：JP32411287
申请日：1987-12-23
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , KANEKO KENJI , NAKAGAWA TETSUYA , UEDA HIROTADA , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/38
摘要： PURPOSE:To improve information processing ability by dividing all control functions into those having the long periods of executing time and others having the short periods respectively and validating the field where the control functions of long periods are described at every other fixed interval of a program address space. CONSTITUTION:An instruction code 201 is divided into a 1st field 202 and a 2nd field 203. The control functions having the short period of executing time are described in the field 202 together with the control functions having the long periods described in the field 203 respectively. Thus the instruction executing intervals are different from each other at every field and therefore the address signals 112 and 113 supplied to address decoders 103 and 104 respectively have different types from each other. Furthermore the instruction codes 116 and 117 have different types of instruction executing timing for separate production of timing signals 115 and 114 respectively. In such a way, the executing speeds can be set at every field and therefore the overall processing speed is increased even with a parallel working processor having a long horizontal instruction code.

78. 发明专利

JPS62285152A DATA PROCESSOR 失效
公开(公告)号：JPS62285152A
公开(公告)日：1987-12-11
申请号：JP12790586
申请日：1986-06-04
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , KANEKO KENJI , NAKAGAWA TETSUYA , HAGIWARA YOSHIMUNE , SAWASE TERUMI , NAKAMURA HIDEO
IPC分类号： G06F9/32 , G06F12/02 , G06F12/06 , G06F13/16
摘要： PURPOSE:To minimize the unused area of a built-in memory by dividing the area of said memory into plural pages and providing a function to each page to designate the application for instruction or data. CONSTITUTION:A group of instructions to be executed are stored in an external memory 603. The output 604 of a program counter 602 is outputted to the outside and an instruction is fetched by an internal instruction bus 106 from the memory 603. When this instruction designates an instruction or data of a memory area, the instruction code on the bus 106 is decoded by a decoder 601 and the outputs are sent to the control outputs 109a-109e of a control circuit 108a. Thus the pages of a memory 104 can be optionally designated for instructions or data. Therefore, the memory areas can be properly distributed for application even though the buses of both instruction and data systems are set independently of each other and the memory areas to store instructions are separated from those to store data.

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